Commit c7ff7be6 authored by Yong Zhao's avatar Yong Zhao Committed by Alex Deucher
Browse files

drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to use 



kfd has the same need to set the VM page table base register, so expose
them for kfd to use for better maintainability.

Signed-off-by: default avatarYong Zhao <Yong.Zhao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4f85940

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+12 −7
Original line number Diff line number Diff line
@@ -35,20 +35,25 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 
	return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

}



static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)

void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base)

{

	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);

	/* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */

	int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32

			- mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;



	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

		     lower_32_bits(value));

	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

				offset * vmid, lower_32_bits(page_table_base));



	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

		     upper_32_bits(value));

	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

				offset * vmid, upper_32_bits(page_table_base));

}



static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)

{

	gfxhub_v1_0_init_gart_pt_regs(adev);

	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);



	gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);



	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

		     (u32)(adev->gmc.gart_start >> 12));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h

+6 −0
Original line number Diff line number Diff line
@@ -27,4 +27,10 @@ 
extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;

extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;



/* amdgpu_amdkfd*.c */

void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base);

void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base);



#endif

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+12 −7
Original line number Diff line number Diff line
@@ -52,20 +52,25 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 
	return base;

}



static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)

void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base)

{

	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);

	/* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */

	int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32

			- mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;



	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

		     lower_32_bits(value));

	WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

			offset * vmid, lower_32_bits(page_table_base));



	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

		     upper_32_bits(value));

	WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

			offset * vmid, upper_32_bits(page_table_base));

}



static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)

{

	mmhub_v1_0_init_gart_pt_regs(adev);

	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);



	mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);



	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

		     (u32)(adev->gmc.gart_start >> 12));

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