drm/i915: Use ring->flush() instead of MI_FLUSH (c7f9f9a8) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_drv.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -1001,6 +1001,10 @@ void i915_gem_retire_requests(struct drm_device *dev);
		void i915_gem_reset_flushing_list(struct drm_device *dev);
		void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev);
		void i915_gem_clflush_object(struct drm_gem_object *obj);
		void i915_gem_flush_ring(struct drm_device *dev,
		struct intel_ring_buffer *ring,
		uint32_t invalidate_domains,
		uint32_t flush_domains);
		int i915_gem_object_set_domain(struct drm_gem_object *obj,
		uint32_t read_domains,
		uint32_t write_domain);

+1 −1

Original line number	Diff line number	Diff line
		@@ -1908,7 +1908,7 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno,
		return i915_do_wait_request(dev, seqno, 1, ring);
		}

		static void
		void
		i915_gem_flush_ring(struct drm_device *dev,
		struct intel_ring_buffer *ring,
		uint32_t invalidate_domains,

+15 −16

Original line number	Diff line number	Diff line
		@@ -5056,24 +5056,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
		atomic_inc(&obj_priv->pending_flip);
		work->pending_flip_obj = obj;

		if (was_dirty \|\| IS_GEN3(dev) \|\| IS_GEN2(dev)) {
		BEGIN_LP_RING(2);
		/* Schedule the pipelined flush */
		if (was_dirty)
		i915_gem_flush_ring(dev, obj_priv->ring, 0, was_dirty);

		if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {
		u32 flip_mask;

		/* Can't queue multiple flips, so wait for the previous
		* one to finish before executing the next.
		*/

		BEGIN_LP_RING(2);
		if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

		OUT_RING(MI_WAIT_FOR_EVENT \| flip_mask);
		} else
		OUT_RING(MI_NOOP);
		OUT_RING(MI_FLUSH);
		ADVANCE_LP_RING();
		}