Commit c7f54d21 authored by Aravind Gopalakrishnan's avatar Aravind Gopalakrishnan Committed by Ingo Molnar
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x86/mce: Add a Scalable MCA vendor flags bit 



Scalable MCA (SMCA) is a new feature in AMD Fam17h processors
which indicates presence of MCA extensions.

MCA extensions expands existing register space for the MCE banks
and also introduces a new MSR range to accommodate new banks.

Add the detection bit.

Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
[ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ]
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 79ebdc95

arch/x86/include/asm/mce.h

+21 −13
Original line number Original line Diff line number Diff line
@@ -124,18 +124,26 @@ struct mca_config { 




struct mce_vendor_flags {

struct mce_vendor_flags {

	/*

	/*

			 * overflow recovery cpuid bit indicates that overflow

	 * Indicates that overflow conditions are not fatal, when set.

			 * conditions are not fatal

	 */

	 */

	__u64 overflow_recov	: 1,

	__u64 overflow_recov	: 1,





	/*

	/*

			 * SUCCOR stands for S/W UnCorrectable error COntainment

	 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and

			 * and Recovery. It indicates support for data poisoning

	 * Recovery. It indicates support for data poisoning in HW and deferred

			 * in HW and deferred error interrupts.

	 * error interrupts.

	 */

	 */

	      succor		: 1,

	      succor		: 1,

			__reserved_0	: 62;



	/*

	 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands

	 * the register space for each MCA bank and also increases number of

	 * banks. Also, to accommodate the new banks and registers, the MCA

	 * register space is moved to a new MSR range.

	 */

	      smca		: 1,



	      __reserved_0	: 61;

};

};

extern struct mce_vendor_flags mce_flags;

extern struct mce_vendor_flags mce_flags;

arch/x86/kernel/cpu/mcheck/mce.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 
		mce_amd_feature_init(c);

		mce_amd_feature_init(c);

		mce_flags.overflow_recov = !!(ebx & BIT(0));

		mce_flags.overflow_recov = !!(ebx & BIT(0));

		mce_flags.succor	 = !!(ebx & BIT(1));

		mce_flags.succor	 = !!(ebx & BIT(1));

		mce_flags.smca		 = !!(ebx & BIT(3));



		break;

		break;

		}

		}

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