Commit c7f345e5 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: initialize get_max_link_cap 



[why]
usb3->usb2 switch system hang.
driver needs to limit the max sink cap based on DP4 mode.

[how]
based on s_dpalt check and DP4 check:
limit the USB-C DPALT DP maximum supported lane count.

Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa90219a

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c

+24 −0
Original line number Diff line number Diff line
@@ -311,6 +311,28 @@ void enc2_hw_init(struct link_encoder *enc) 
	dcn10_aux_initialize(enc10);

}



void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,

	struct dc_link_settings *link_settings)

{

	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	uint32_t value;



	REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);



	if (!value && link_settings->lane_count > LANE_COUNT_TWO)

		link_settings->lane_count = LANE_COUNT_TWO;

}

bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)

{

	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	uint32_t value;



	REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);



	// if value == 1 alt mode is disabled, otherwise it is enabled

	return !value;

}



static const struct link_encoder_funcs dcn20_link_enc_funcs = {

	.read_state = link_enc2_read_state,

	.validate_output_with_stream =
@@ -338,6 +360,8 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = { 
	.fec_is_active = enc2_fec_is_active,

	.get_dig_mode = dcn10_get_dig_mode,

	.get_dig_frontend = dcn10_get_dig_frontend,

	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,

	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,

};



void dcn20_link_encoder_construct(

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