Commit c7ec75ea authored Aug 14, 2019 by Dinh Nguyen Committed by Stephen Boyd Aug 14, 2019

clk: socfpga: stratix10: fix rate caclulationg for cnt_clks



Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.

Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org


Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent baf7b79e

drivers/clk/socfpga/clk-periph-s10.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
		if (socfpgaclk->fixed_div) {
		div = socfpgaclk->fixed_div;
		} else {
		if (!socfpgaclk->bypass_reg)
		if (socfpgaclk->hw.reg)
		div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
		}

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