Commit c7b68049 authored Aug 09, 2019 by Arnd Bergmann

ARM: xscale: fix multi-cpu compilation

Building a combined ARMv4+XScale kernel produces these
and other build failures:

/tmp/copypage-xscale-3aa821.s: Assembler messages:
/tmp/copypage-xscale-3aa821.s:167: Error: selected processor does not support `pld [r7,#0]' in ARM mode
/tmp/copypage-xscale-3aa821.s:168: Error: selected processor does not support `pld [r7,#32]' in ARM mode
/tmp/copypage-xscale-3aa821.s:169: Error: selected processor does not support `pld [r1,#0]' in ARM mode
/tmp/copypage-xscale-3aa821.s:170: Error: selected processor does not support `pld [r1,#32]' in ARM mode
/tmp/copypage-xscale-3aa821.s:171: Error: selected processor does not support `pld [r7,#64]' in ARM mode
/tmp/copypage-xscale-3aa821.s:176: Error: selected processor does not support `ldrd r4,r5,[r7],#8' in ARM mode
/tmp/copypage-xscale-3aa821.s:180: Error: selected processor does not support `strd r4,r5,[r1],#8' in ARM mode

Add an explict .arch armv5 in the inline assembly to allow the ARMv5
specific instructions regardless of the compiler -march= target.

Link: https://lore.kernel.org/r/20190809163334.489360-5-arnd@arndb.de


Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent aad7ad2a

arch/arm/mm/copypage-xscale.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@ static void mc_copy_user_page(void from, void to)
		* when prefetching destination as well. (NP)
		*/
		asm volatile ("\
		.arch xscale \n\
		pld [%0, #0] \n\
		pld [%0, #32] \n\
		pld [%1, #0] \n\
		@@ -106,8 +107,9 @@ void
		xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
		{
		void ptr, kaddr = kmap_atomic(page);
		asm volatile(
		"mov r1, %2 \n\
		asm volatile("\
		.arch xscale \n\
		mov r1, %2 \n\
		mov r2, #0 \n\
		mov r3, #0 \n\
		1: mov ip, %0 \n\

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