Commit c79a14de authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:
 "This last cycle, Thor was busy adding Arria10 eth FIFO support to the
  altera_edac driver along with other improvements.  We have two
  cleanups/fixes too.

  Summary:

   - Altera Arria10 ethernet FIFO buffer support (Thor Thayer)

   - Minor cleanups"

* tag 'edac_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  ARM: dts: Add Arria10 Ethernet EDAC devicetree entry
  EDAC, altera: Add Arria10 Ethernet EDAC support
  EDAC, altera: Add Arria10 ECC memory init functions
  Documentation: dt: socfpga: Add Arria10 Ethernet binding
  EDAC, altera: Drop some ifdeffery
  EDAC, altera: Add panic flag check to A10 IRQ
  EDAC, altera: Check parent status for Arria10 EDAC block
  EDAC, altera: Make all private data structures static
  EDAC: Correct channel count limit
  EDAC, amd64_edac: Init opstate at the proper time during init
  EDAC, altera: Handle Arria10 SDRAM child node
  EDAC, altera: Add ECC Manager IRQ controller support
  Documentation: dt: socfpga: Add interrupt-controller to ecc-manager
parents 6e8d666e a67adb32

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

+37 −1
Original line number Diff line number Diff line
@@ -61,7 +61,9 @@ Required Properties: 
- #address-cells: must be 1

- #size-cells: must be 1

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.

	interrupt.

- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller

- #interrupt-cells : must be set to 2.

- ranges : standard definition, should translate from local addresses



Subcomponents:
@@ -70,11 +72,23 @@ L2 Cache ECC 
Required Properties:

- compatible : Should be "altr,socfpga-a10-l2-ecc"

- reg : Address and size for ECC error interrupt clear registers.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt, in this order.



On-Chip RAM ECC

Required Properties:

- compatible : Should be "altr,socfpga-a10-ocram-ecc"

- reg        : Address and size for ECC block registers.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt, in this order.



Ethernet FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-eth-mac-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent Ethernet node.

- interrupts      : Should be single bit error interrupt, then double bit error

	interrupt, in this order.



Example:
@@ -85,15 +99,37 @@ Example: 
		#size-cells = <1>;

		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,

			     <0 0 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ranges;



		l2-ecc@ffd06010 {

			compatible = "altr,socfpga-a10-l2-ecc";

			reg = <0xffd06010 0x4>;

			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,

				     <32 IRQ_TYPE_LEVEL_HIGH>;

		};



		ocram-ecc@ff8c3000 {

			compatible = "altr,socfpga-a10-ocram-ecc";

			reg = <0xff8c3000 0x90>;

			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,

				     <33 IRQ_TYPE_LEVEL_HIGH> ;

		};



		emac0-rx-ecc@ff8c0800 {

			compatible = "altr,socfpga-eth-mac-ecc";

			reg = <0xff8c0800 0x400>;

			altr,ecc-parent = <&gmac0>;

			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,

				     <36 IRQ_TYPE_LEVEL_HIGH>;

		};



		emac0-tx-ecc@ff8c0c00 {

			compatible = "altr,socfpga-eth-mac-ecc";

			reg = <0xff8c0c00 0x400>;

			altr,ecc-parent = <&gmac0>;

			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,

				     <37 IRQ_TYPE_LEVEL_HIGH>;

		};

	};

arch/arm/boot/dts/socfpga_arria10.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -621,6 +621,22 @@ 
				compatible = "altr,socfpga-a10-ocram-ecc";

				reg = <0xff8c3000 0x400>;

			};



			emac0-rx-ecc@ff8c0800 {

				compatible = "altr,socfpga-eth-mac-ecc";

				reg = <0xff8c0800 0x400>;

				altr,ecc-parent = <&gmac0>;

				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,

					     <36 IRQ_TYPE_LEVEL_HIGH>;

			};



			emac0-tx-ecc@ff8c0c00 {

				compatible = "altr,socfpga-eth-mac-ecc";

				reg = <0xff8c0c00 0x400>;

				altr,ecc-parent = <&gmac0>;

				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,

					     <37 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		rst: rstmgr@ffd05000 {

drivers/edac/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM 
	  Support for error detection and correction on the

	  Altera On-Chip RAM Memory for Altera SoCs.



config EDAC_ALTERA_ETHERNET

	bool "Altera Ethernet FIFO ECC"

	depends on EDAC_ALTERA=y

	help

	  Support for error detection and correction on the

	  Altera Ethernet FIFO Memory for Altera SoCs.



config EDAC_SYNOPSYS

	tristate "Synopsys DDR Memory Controller"

	depends on EDAC_MM_EDAC && ARCH_ZYNQ

drivers/edac/altera_edac.c

+423 −69

File changed.

Preview size limit exceeded, changes collapsed.

drivers/edac/altera_edac.h

+15 −2
Original line number Diff line number Diff line
@@ -230,8 +230,13 @@ struct altr_sdram_mc_data { 
#define ALTR_A10_ECC_INITCOMPLETEB      BIT(8)



#define ALTR_A10_ECC_ERRINTEN_OFST      0x10

#define ALTR_A10_ECC_ERRINTENS_OFST     0x14

#define ALTR_A10_ECC_ERRINTENR_OFST     0x18

#define ALTR_A10_ECC_SERRINTEN          BIT(0)



#define ALTR_A10_ECC_INTMODE_OFST       0x1C

#define ALTR_A10_ECC_INTMODE            BIT(0)



#define ALTR_A10_ECC_INTSTAT_OFST       0x20

#define ALTR_A10_ECC_SERRPENA           BIT(0)

#define ALTR_A10_ECC_DERRPENA           BIT(8)
@@ -280,6 +285,12 @@ struct altr_sdram_mc_data { 
/* Arria 10 OCRAM ECC Management Group Defines */

#define ALTR_A10_OCRAM_ECC_EN_CTL       (BIT(1) | BIT(0))



/* Arria 10 Ethernet ECC Management Group Defines */

#define ALTR_A10_COMMON_ECC_EN_CTL      BIT(0)



/* A10 ECC Controller memory initialization timeout */

#define ALTR_A10_ECC_INIT_WATCHDOG_10US      10000



struct altr_edac_device_dev;



struct edac_device_prv_data {
@@ -295,10 +306,10 @@ struct edac_device_prv_data { 
	int ce_set_mask;

	int ue_set_mask;

	int set_err_ofst;

	irqreturn_t (*ecc_irq_handler)(struct altr_edac_device_dev *dci,

				       bool sb);

	irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);

	int trig_alloc_sz;

	const struct file_operations *inject_fops;

	bool panic;

};



struct altr_edac_device_dev {
@@ -320,6 +331,8 @@ struct altr_arria10_edac { 
	struct regmap		*ecc_mgr_map;

	int sb_irq;

	int db_irq;

	struct irq_domain	*domain;

	struct irq_chip		irq_chip;

	struct list_head	a10_ecc_devices;

};

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