Commit c788739b authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add wm ranges to clk_mgr 



[WHY & HOW]
Having watermark ranges saved inside clk_mgr to be
available for debug at all times would be useful.
Add it to the clk_mgr_internal struct for reference.
Only populated for Renoir, unused for other asics.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 32caf906

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+2 −3
Original line number Diff line number Diff line
@@ -459,16 +459,15 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra 
static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

{

	struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;

	struct pp_smu_wm_range_sets ranges = {0};

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;



	if (!debug->disable_pplib_wm_range) {

		build_watermark_ranges(clk_mgr_base->bw_params, &ranges);

		build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);



		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */

		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)

			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);

			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);

	}



}

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define __DAL_CLK_MGR_H__



#include "dc.h"

#include "dm_pp_smu.h"



#define DCN_MINIMUM_DISPCLK_Khz 100000

#define DCN_MINIMUM_DPPCLK_Khz 100000
@@ -193,6 +194,7 @@ struct clk_mgr { 
	int dentist_vco_freq_khz;

	struct clk_state_registers_and_bypass boot_snapshot;

	struct clk_bw_params *bw_params;

	struct pp_smu_wm_range_sets ranges;

};



/* forward declarations */

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