Commit c77a4de2 authored by Linus Walleij's avatar Linus Walleij
Browse files

pinctrl: st: Pass irqchip when adding gpiochip 



We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion: the ST pin controller errors out of adding a
irqchip if the interrupt is invalid or missing or if the
irqmux is not present: the irqchip should not be added
if either of these errors happen, so rewrite the code to
deal with that. Keep the exit path where the gpio_chip
is added no matter what the status of the irq is.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191001135147.29416-1-linus.walleij@linaro.org
parent 35dea5d7

drivers/pinctrl/pinctrl-st.c

+32 −21
Original line number Diff line number Diff line
@@ -1477,7 +1477,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, 
	struct device *dev = info->dev;

	int bank_num = of_alias_get_id(np, "gpio");

	struct resource res, irq_res;

	int gpio_irq = 0, err;

	int err;



	if (of_address_to_resource(np, 0, &res))

		return -ENODEV;
@@ -1500,12 +1500,6 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, 
	range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;

	range->npins = bank->gpio_chip.ngpio;

	range->gc = &bank->gpio_chip;

	err  = gpiochip_add_data(&bank->gpio_chip, bank);

	if (err) {

		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);

		return err;

	}

	dev_info(dev, "%s bank added.\n", range->name);



	/**

	 * GPIO bank can have one of the two possible types of
@@ -1527,23 +1521,40 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, 
	 */



	if (of_irq_to_resource(np, 0, &irq_res) > 0) {

		gpio_irq = irq_res.start;

		gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,

					     gpio_irq, st_gpio_irq_handler);

		struct gpio_irq_chip *girq;

		int gpio_irq = irq_res.start;



		/* This is not a valid IRQ */

		if (gpio_irq <= 0) {

			dev_err(dev, "invalid IRQ for %pOF bank\n", np);

			goto skip_irq;

		}

		/* We need to have a mux as well */

		if (!info->irqmux_base) {

			dev_err(dev, "no irqmux for %pOF bank\n", np);

			goto skip_irq;

		}



	if (info->irqmux_base || gpio_irq > 0) {

		err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,

					   0, handle_simple_irq,

					   IRQ_TYPE_NONE);

		girq = &bank->gpio_chip.irq;

		girq->chip = &st_gpio_irqchip;

		girq->parent_handler = st_gpio_irq_handler;

		girq->num_parents = 1;

		girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),

					     GFP_KERNEL);

		if (!girq->parents)

			return -ENOMEM;

		girq->parents[0] = gpio_irq;

		girq->default_type = IRQ_TYPE_NONE;

		girq->handler = handle_simple_irq;

	}



skip_irq:

	err  = gpiochip_add_data(&bank->gpio_chip, bank);

	if (err) {

			gpiochip_remove(&bank->gpio_chip);

			dev_info(dev, "could not add irqchip\n");

		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);

		return err;

	}

	} else {

		dev_info(dev, "No IRQ support for %pOF bank\n", np);

	}

	dev_info(dev, "%s bank added.\n", range->name);



	return 0;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE