Commit c746063a authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi
Browse files

drm/i915: Implement WA 14011294188 



Although the WA description targets the platforms it is a workaround
for the affected PCHs, that is why it is being checked.

v2: excluding DG1 fake PCH from WA

BSpec: 52890
BSpec: 53273
BSpec: 52888
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200727164729.28836-1-jose.souza@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 90e13292

drivers/gpu/drm/i915/display/intel_display_power.c

+6 −0
Original line number Diff line number Diff line
@@ -5302,6 +5302,12 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, 


	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	/* Wa_14011294188:ehl,jsl,tgl,rkl */

	if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&

	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)

		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,

			     PCH_DPMGUNIT_CLOCK_GATE_DISABLE);



	/* 1. Enable PCH reset handshake. */

	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -8730,6 +8730,7 @@ enum { 
#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)

#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)

#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)

#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)

#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)

#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)

#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)

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