Commit c72cd19f authored by Ben Cahill's avatar Ben Cahill Committed by John W. Linville
Browse files

iwlagn: Clarify FH_TX interrupt



Add/clarify comments and debug messages for interrupt used only for uCode load

Signed-off-by: default avatarBen Cahill <ben.m.cahill@intel.com>
Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent a6c5c731
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+6 −4
Original line number Diff line number Diff line
@@ -1033,11 +1033,12 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
		handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
	}

	/* This "Tx" DMA channel is used only for loading uCode */
	if (inta & CSR_INT_BIT_FH_TX) {
		IWL_DEBUG_ISR(priv, "Tx interrupt\n");
		IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
		priv->isr_stats.tx++;
		handled |= CSR_INT_BIT_FH_TX;
		/* FH finished to write, send event */
		/* Wake up uCode load routine, now that load is complete */
		priv->ucode_write_complete = 1;
		wake_up_interruptible(&priv->wait_command_queue);
	}
@@ -1234,12 +1235,13 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
		iwl_leds_background(priv);
	}

	/* This "Tx" DMA channel is used only for loading uCode */
	if (inta & CSR_INT_BIT_FH_TX) {
		iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
		IWL_DEBUG_ISR(priv, "Tx interrupt\n");
		IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
		priv->isr_stats.tx++;
		handled |= CSR_INT_BIT_FH_TX;
		/* FH finished to write, send event */
		/* Wake up uCode load routine, now that load is complete */
		priv->ucode_write_complete = 1;
		wake_up_interruptible(&priv->wait_command_queue);
	}