Commit c70c4733 authored Mar 29, 2017 by Alexey Brodkin Committed by Vineet Gupta Mar 30, 2017

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing



As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)

Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.

Cc: stable@vger.kernel.org  #4.10
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
[vgupta: reworte changelog a bit]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

parent ae9955ae

arch/arc/mm/cache.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -633,6 +633,9 @@ noinline static void slc_entire_op(const int op)

		write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);

		/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
		read_aux_reg(r);

		/* Important to wait for flush to complete */
		while (read_aux_reg(r) & SLC_CTRL_BUSY);
		}

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