Commit c709feda authored by Ingo Molnar's avatar Ingo Molnar
Browse files

x86/mm/pat: Initialize __cachemode2pte_tbl[] and __pte2cachemode_tbl[] in a... 


x86/mm/pat: Initialize __cachemode2pte_tbl[] and __pte2cachemode_tbl[] in a bit more readable fashion

The initialization of these two arrays is a bit difficult to follow:
restructure it optically so that a 2D structure shows which bit in
the PTE is set and which not.

Also improve on comments a bit.

No code or data changed:

  # arch/x86/mm/init.o:

   text    data     bss     dec     hex filename
   4585     424   29776   34785    87e1 init.o.before
   4585     424   29776   34785    87e1 init.o.after

md5:
   a82e11ff58bcfd0af3a94662a701f65d  init.o.before.asm
   a82e11ff58bcfd0af3a94662a701f65d  init.o.after.asm

Reviewed-by: default avatarJuergen Gross <jgross@suse.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jan Beulich <JBeulich@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Toshi Kani <toshi.kani@hp.com>
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/20150305082135.GB5969@gmail.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent c281b945

arch/x86/mm/init.c

+22 −18
Original line number Diff line number Diff line
@@ -29,29 +29,33 @@ 


/*

 * Tables translating between page_cache_type_t and pte encoding.

 * Minimal supported modes are defined statically, modified if more supported

 * cache modes are available.

 * Index into __cachemode2pte_tbl is the cachemode.

 * Index into __pte2cachemode_tbl are the caching attribute bits of the pte

 *

 * Minimal supported modes are defined statically, they are modified

 * during bootup if more supported cache modes are available.

 *

 *   Index into __cachemode2pte_tbl[] is the cachemode.

 *

 *   Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte

 *   (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.

 */

uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {

	[_PAGE_CACHE_MODE_WB]		= 0,

	[_PAGE_CACHE_MODE_WC]		= _PAGE_PWT,

	[_PAGE_CACHE_MODE_UC_MINUS]	= _PAGE_PCD,

	[_PAGE_CACHE_MODE_UC]		= _PAGE_PCD | _PAGE_PWT,

	[_PAGE_CACHE_MODE_WT]		= _PAGE_PCD,

	[_PAGE_CACHE_MODE_WP]		= _PAGE_PCD,

	[_PAGE_CACHE_MODE_WB      ]	= 0         | 0        ,

	[_PAGE_CACHE_MODE_WC      ]	= _PAGE_PWT | 0        ,

	[_PAGE_CACHE_MODE_UC_MINUS]	= 0         | _PAGE_PCD,

	[_PAGE_CACHE_MODE_UC      ]	= _PAGE_PWT | _PAGE_PCD,

	[_PAGE_CACHE_MODE_WT      ]	= 0         | _PAGE_PCD,

	[_PAGE_CACHE_MODE_WP      ]	= 0         | _PAGE_PCD,

};

EXPORT_SYMBOL(__cachemode2pte_tbl);



uint8_t __pte2cachemode_tbl[8] = {

	[__pte2cm_idx(0)] = _PAGE_CACHE_MODE_WB,

	[__pte2cm_idx(_PAGE_PWT)] = _PAGE_CACHE_MODE_WC,

	[__pte2cm_idx(_PAGE_PCD)] = _PAGE_CACHE_MODE_UC_MINUS,

	[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD)] = _PAGE_CACHE_MODE_UC,

	[__pte2cm_idx(_PAGE_PAT)] = _PAGE_CACHE_MODE_WB,

	[__pte2cm_idx(_PAGE_PWT | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,

	[__pte2cm_idx(_PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,

	[__pte2cm_idx( 0        | 0         | 0        )] = _PAGE_CACHE_MODE_WB,

	[__pte2cm_idx(_PAGE_PWT | 0         | 0        )] = _PAGE_CACHE_MODE_WC,

	[__pte2cm_idx( 0        | _PAGE_PCD | 0        )] = _PAGE_CACHE_MODE_UC_MINUS,

	[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0        )] = _PAGE_CACHE_MODE_UC,

	[__pte2cm_idx( 0        | 0         | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,

	[__pte2cm_idx(_PAGE_PWT | 0         | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,

	[__pte2cm_idx(0         | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,

	[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,

};

EXPORT_SYMBOL(__pte2cachemode_tbl);

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