Commit c6f7acb8 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/ehl: Introduce Mule Creek Canyon PCH 



Although EHL introduces a new PCH, the South Display part of the PCH
that we care about is nearly identical to ICP, just with some pins
remapped.  Most notably, Port C is mapped to the pins that ICP uses for
TC Port 1.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190615004210.16656-1-matthew.d.roper@intel.com
parent 32a19631

drivers/gpu/drm/i915/display/intel_bios.c

+10 −1
Original line number Diff line number Diff line
@@ -1348,12 +1348,21 @@ static const u8 icp_ddc_pin_map[] = { 
	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,

};



static const u8 mcc_ddc_pin_map[] = {

	[MCC_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,

	[MCC_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,

	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,

};



static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)

{

	const u8 *ddc_pin_map;

	int n_entries;



	if (HAS_PCH_ICP(dev_priv)) {

	if (HAS_PCH_MCC(dev_priv)) {

		ddc_pin_map = mcc_ddc_pin_map;

		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);

	} else if (HAS_PCH_ICP(dev_priv)) {

		ddc_pin_map = icp_ddc_pin_map;

		n_entries = ARRAY_SIZE(icp_ddc_pin_map);

	} else if (HAS_PCH_CNP(dev_priv)) {

drivers/gpu/drm/i915/display/intel_gmbus.c

+12 −2
Original line number Diff line number Diff line
@@ -88,11 +88,19 @@ static const struct gmbus_pin gmbus_pins_icp[] = { 
	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },

};



static const struct gmbus_pin gmbus_pins_mcc[] = {

	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },

	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },

	[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },

};



/* pin is expected to be valid */

static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,

					     unsigned int pin)

{

	if (HAS_PCH_ICP(dev_priv))

	if (HAS_PCH_MCC(dev_priv))

		return &gmbus_pins_mcc[pin];

	else if (HAS_PCH_ICP(dev_priv))

		return &gmbus_pins_icp[pin];

	else if (HAS_PCH_CNP(dev_priv))

		return &gmbus_pins_cnp[pin];
@@ -111,7 +119,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 
{

	unsigned int size;



	if (HAS_PCH_ICP(dev_priv))

	if (HAS_PCH_MCC(dev_priv))

		size = ARRAY_SIZE(gmbus_pins_mcc);

	else if (HAS_PCH_ICP(dev_priv))

		size = ARRAY_SIZE(gmbus_pins_icp);

	else if (HAS_PCH_CNP(dev_priv))

		size = ARRAY_SIZE(gmbus_pins_cnp);

drivers/gpu/drm/i915/display/intel_hdmi.c

+25 −1
Original line number Diff line number Diff line
@@ -2959,6 +2959,28 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 
	return ddc_pin;

}



static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)

{

	u8 ddc_pin;



	switch (port) {

	case PORT_A:

		ddc_pin = GMBUS_PIN_1_BXT;

		break;

	case PORT_B:

		ddc_pin = GMBUS_PIN_2_BXT;

		break;

	case PORT_C:

		ddc_pin = GMBUS_PIN_9_TC1_ICP;

		break;

	default:

		MISSING_CASE(port);

		ddc_pin = GMBUS_PIN_1_BXT;

		break;

	}

	return ddc_pin;

}



static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,

			      enum port port)

{
@@ -2995,7 +3017,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 
		return info->alternate_ddc_pin;

	}



	if (HAS_PCH_ICP(dev_priv))

	if (HAS_PCH_MCC(dev_priv))

		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);

	else if (HAS_PCH_ICP(dev_priv))

		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);

	else if (HAS_PCH_CNP(dev_priv))

		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);

drivers/gpu/drm/i915/display/intel_vbt_defs.h

+3 −0
Original line number Diff line number Diff line
@@ -314,6 +314,9 @@ enum vbt_gmbus_ddi { 
	ICL_DDC_BUS_PORT_2,

	ICL_DDC_BUS_PORT_3,

	ICL_DDC_BUS_PORT_4,

	MCC_DDC_BUS_DDI_A = 0x1,

	MCC_DDC_BUS_DDI_B,

	MCC_DDC_BUS_DDI_C = 0x4,

};



#define DP_AUX_A 0x40

drivers/gpu/drm/i915/i915_drv.c

+7 −1
Original line number Diff line number Diff line
@@ -218,6 +218,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) 
		DRM_DEBUG_KMS("Found Ice Lake PCH\n");

		WARN_ON(!IS_ICELAKE(dev_priv));

		return PCH_ICP;

	case INTEL_PCH_MCC_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");

		WARN_ON(!IS_ELKHARTLAKE(dev_priv));

		return PCH_MCC;

	default:

		return PCH_NONE;

	}
@@ -245,7 +249,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) 
	 * make an educated guess as to which PCH is really there.

	 */



	if (IS_ICELAKE(dev_priv))

	if (IS_ELKHARTLAKE(dev_priv))

		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;

	else if (IS_ICELAKE(dev_priv))

		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;

	else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))

		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;

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