Commit c6ef8942 authored Sep 01, 2017 by Ingo Molnar Committed by Thomas Gleixner Sep 01, 2017

x86/idt: Fix the X86_TRAP_BP gate



Andrei Vagin reported a CRIU regression and bisected it back to:

  90f6225f ("x86/idt: Move IST stack based traps to table init")

This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.

Fix it.

Reported-by: Andrei Vagin <avagin@virtuozzo.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: dvlasenk@redhat.com
Cc: linux-tip-commits@vger.kernel.org
Cc: peterz@infradead.org
Cc: brgerst@gmail.com
Cc: rostedt@goodmis.org
Cc: bp@alien8.de
Cc: luto@kernel.org
Cc: jpoimboe@redhat.com
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: torvalds@linux-foundation.org
Cc: tip-bot for Jacob Shin <tipbot@zytor.com>
Link: http://lkml.kernel.org/r/20170901082630.xvyi5bwk6etmppqc@gmail.com

parent 5878d5d6

arch/x86/kernel/idt.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -44,6 +44,10 @@ struct idt_data {
		#define ISTG(_vector, _addr, _ist) \
		G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)

		/* System interrupt gate with interrupt stack */
		#define SISTG(_vector, _addr, _ist) \
		G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)

		/* Task gate */
		#define TSKG(_vector, _gdt) \
		G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
		@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
		static const __initdata struct idt_data ist_idts[] = {
		ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
		ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
		ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
		SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
		ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
		#ifdef CONFIG_X86_MCE
		ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),

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