Commit c635a815 authored by Manikanta Maddireddy's avatar Manikanta Maddireddy Committed by Lorenzo Pieralisi
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PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability



Default root port setting hides AER capability. This patch enables the
advertisement of AER capability by root port.

Signed-off-by: default avatarManikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
parent 538123a2
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+15 −0
Original line number Diff line number Diff line
@@ -180,6 +180,9 @@
#define RP_VEND_XP	0x00000f00
#define  RP_VEND_XP_DL_UP	(1 << 30)

#define RP_VEND_CTL1	0x00000f48
#define  RP_VEND_CTL1_ERPT	(1 << 13)

#define RP_VEND_CTL2 0x00000fa8
#define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)

@@ -479,6 +482,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
	afi_writel(port->pcie, value, ctrl);
}

static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
{
	u32 value;

	/* Enable AER capability */
	value = readl(port->base + RP_VEND_CTL1);
	value |= RP_VEND_CTL1_ERPT;
	writel(value, port->base + RP_VEND_CTL1);
}

static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{
	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@@ -503,6 +516,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
		value |= RP_VEND_CTL2_PCA_ENABLE;
		writel(value, port->base + RP_VEND_CTL2);
	}

	tegra_pcie_enable_rp_features(port);
}

static void tegra_pcie_port_disable(struct tegra_pcie_port *port)