xtensa: initialize atomctl SR

We Have Atomic Operation Control (ATOMCTL) Register.

This register determines the effect of using a S32C1I instruction

with various combinations of:

     1. With and without an Coherent Cache Controller which

        can do Atomic Transactions to the memory internally.

     2. With and without An Intelligent Memory Controller which

        can do Atomic Transactions itself.

The Core comes up with a default value of for the three types of cache ops:

      0x28: (WB: Internal, WT: Internal, BY:Exception)

On the FPGA Cards we typically simulate an Intelligent Memory controller

which can implement  RCW transactions. For FPGA cards with an External

Memory controller we let it to the atomic operations internally while

doing a Cached (WB) transaction and use the Memory RCW for un-cached

operations.

For systems without an coherent cache controller, non-MX, we always

use the memory controllers RCW, thought non-MX controlers likely

support the Internal Operation.

CUSTOMER-WARNING:

   Virtually all customers buy their memory controllers from vendors that

   don't support atomic RCW memory transactions and will likely want to

   configure this register to not use RCW.

Developers might find using RCW in Bypass mode convenient when testing

with the cache being bypassed; for example studying cache alias problems.

See Section 4.3.12.4 of ISA; Bits:

                             WB     WT      BY

                           5   4 | 3   2 | 1   0

  2 Bit

  Field

  Values     WB - Write Back         WT - Write Thru         BY - Bypass

---------    ---------------         -----------------     ----------------

    0        Exception               Exception               Exception

    1        RCW Transaction         RCW Transaction         RCW Transaction

    2        Internal Operation      Exception               Reserved

    3        Reserved                Reserved                Reserved

/*

 * arch/xtensa/include/asm/initialize_mmu.h

 *

 * Initializes MMU:

 *

 *      For the new V3 MMU we remap the TLB from virtual == physical

 *      to the standard Linux mapping used in earlier MMU's.

 *

 *      The the MMU we also support a new configuration register that

 *      specifies how the S32C1I instruction operates with the cache

 *      controller.

 *

 * This file is subject to the terms and conditions of the GNU General

 * Public License.  See the file "COPYING" in the main directory of

 * this archive for more details.

 *

 * Copyright (C) 2008 - 2012 Tensilica, Inc.

 *

 *   Marc Gauthier <marc@tensilica.com>

 *   Pete Delaney <piet@tensilica.com>

 */

#ifndef _XTENSA_INITIALIZE_MMU_H

#define _XTENSA_INITIALIZE_MMU_H

#ifdef __ASSEMBLY__

#define XTENSA_HWVERSION_RC_2009_0 230000

	.macro	initialize_mmu

#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)

/*

 * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.

 * For details see Documentation/xtensa/atomctl.txt

 */

#if XCHAL_DCACHE_IS_COHERENT

	movi	a3, 0x25	/* For SMP/MX -- internal for writeback,

				 * RCW otherwise

				 */

#else

	movi	a3, 0x29	/* non-MX -- Most cores use Std Memory

				 * Controlers which usually can't use RCW

				 */

#endif

	wsr	a3, atomctl

#endif  /* XCHAL_HAVE_S32C1I &&

	 * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)

	 */

	.endm

#endif /*__ASSEMBLY__*/

#endif /* _XTENSA_INITIALIZE_MMU_H */

#include <asm/processor.h>

#include <asm/page.h>

#include <asm/cacheasm.h>

#include <asm/initialize_mmu.h>

#include <linux/init.h>

#include <linux/linkage.h>

	isync

	initialize_mmu

	/* Unpack data sections

	 *

	 * The linker script used to build the Linux kernel image