Commit c620f7bd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "Mostly just incremental improvements here:

   - Introduce AT_HWCAP2 for advertising CPU features to userspace

   - Expose SVE2 availability to userspace

   - Support for "data cache clean to point of deep persistence" (DC PODP)

   - Honour "mitigations=off" on the cmdline and advertise status via
     sysfs

   - CPU timer erratum workaround (Neoverse-N1 #1188873)

   - Introduce perf PMU driver for the SMMUv3 performance counters

   - Add config option to disable the kuser helpers page for AArch32 tasks

   - Futex modifications to ensure liveness under contention

   - Rework debug exception handling to seperate kernel and user
     handlers

   - Non-critical fixes and cleanup"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits)
  Documentation: Add ARM64 to kernel-parameters.rst
  arm64/speculation: Support 'mitigations=' cmdline option
  arm64: ssbs: Don't treat CPUs with SSBS as unaffected by SSB
  arm64: enable generic CPU vulnerabilites support
  arm64: add sysfs vulnerability show for speculative store bypass
  arm64: Fix size of __early_cpu_boot_status
  clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters
  clocksource/arm_arch_timer: Remove use of workaround static key
  clocksource/arm_arch_timer: Drop use of static key in arch_timer_reg_read_stable
  clocksource/arm_arch_timer: Direcly assign set_next_event workaround
  arm64: Use arch_timer_read_counter instead of arch_counter_get_cntvct
  watchdog/sbsa: Use arch_timer_read_counter instead of arch_counter_get_cntvct
  ARM: vdso: Remove dependency with the arch_timer driver internals
  arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1
  arm64: Add part number for Neoverse N1
  arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT
  arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32
  arm64: mm: Remove pte_unmap_nested()
  arm64: Fix compiler warning from pte_unmap() with -Wunused-but-set-variable
  arm64: compat: Reduce address limit for 64K pages
  ...
parents dd4e5d61 b33f9088

Documentation/admin-guide/kernel-parameters.rst

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ parameter is applicable:: 
	APIC	APIC support is enabled.

	APM	Advanced Power Management support is enabled.

	ARM	ARM architecture is enabled.

	ARM64	ARM64 architecture is enabled.

	AX25	Appropriate AX.25 support is enabled.

	CLK	Common clock infrastructure is enabled.

	CMA	Contiguous Memory Area support is enabled.

Documentation/admin-guide/kernel-parameters.txt

+9 −7
Original line number Diff line number Diff line
@@ -2548,8 +2548,8 @@ 
			http://repo.or.cz/w/linux-2.6/mini2440.git



	mitigations=

			[X86,PPC,S390] Control optional mitigations for CPU

			vulnerabilities.  This is a set of curated,

			[X86,PPC,S390,ARM64] Control optional mitigations for

			CPU vulnerabilities.  This is a set of curated,

			arch-independent options, each of which is an

			aggregation of existing arch-specific options.
@@ -2558,11 +2558,13 @@ 
				improves system performance, but it may also

				expose users to several CPU vulnerabilities.

				Equivalent to: nopti [X86,PPC]

					       kpti=0 [ARM64]

					       nospectre_v1 [PPC]

					       nobp=0 [S390]

					       nospectre_v2 [X86,PPC,S390]

					       nospectre_v2 [X86,PPC,S390,ARM64]

					       spectre_v2_user=off [X86]

					       spec_store_bypass_disable=off [X86,PPC]

					       ssbd=force-off [ARM64]

					       l1tf=off [X86]



			auto (default)
@@ -2908,10 +2910,10 @@ 
			check bypass). With this option data leaks are possible

			in the system.



	nospectre_v2	[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2

			(indirect branch prediction) vulnerability. System may

			allow data leaks with this option, which is equivalent

			to spectre_v2=off.

	nospectre_v2	[X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for

			the Spectre variant 2 (indirect branch prediction)

			vulnerability. System may allow data leaks with this

			option.



	nospec_store_bypass_disable

			[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

Documentation/arm64/cpu-feature-registers.txt

+16 −0
Original line number Diff line number Diff line
@@ -209,6 +209,22 @@ infrastructure: 
     | AT                           | [35-32] |    y    |

     x--------------------------------------------------x



  6) ID_AA64ZFR0_EL1 - SVE feature ID register 0



     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | SM4                          | [43-40] |    y    |

     |--------------------------------------------------|

     | SHA3                         | [35-32] |    y    |

     |--------------------------------------------------|

     | BitPerm                      | [19-16] |    y    |

     |--------------------------------------------------|

     | AES                          | [7-4]   |    y    |

     |--------------------------------------------------|

     | SVEVer                       | [3-0]   |    y    |

     x--------------------------------------------------x



Appendix I: Example

---------------------------

Documentation/arm64/elf_hwcaps.txt

+38 −3
Original line number Diff line number Diff line
@@ -13,9 +13,9 @@ architected discovery mechanism available to userspace code at EL0. The 
kernel exposes the presence of these features to userspace through a set

of flags called hwcaps, exposed in the auxilliary vector.



Userspace software can test for features by acquiring the AT_HWCAP entry

of the auxilliary vector, and testing whether the relevant flags are

set, e.g.

Userspace software can test for features by acquiring the AT_HWCAP or

AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant

flags are set, e.g.



bool floating_point_is_present(void)

{
@@ -135,6 +135,10 @@ HWCAP_DCPOP 


    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.



HWCAP2_DCPODP



    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP_SHA3



    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
@@ -159,6 +163,30 @@ HWCAP_SVE 


    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.



HWCAP2_SVE2



    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.



HWCAP2_SVEAES



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM



    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3



    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4



    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP_ASIMDFHM



   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
@@ -194,3 +222,10 @@ HWCAP_PACG 
    Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or

    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by

    Documentation/arm64/pointer-authentication.txt.





4. Unused AT_HWCAP bits

-----------------------



For interoperation with userspace, the kernel guarantees that bits 62

and 63 of AT_HWCAP will always be returned as 0.

Documentation/arm64/silicon-errata.txt

+2 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ stable kernels. 
| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | Neoverse-N1     | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |
@@ -77,6 +78,7 @@ stable kernels. 
| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

| Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |

|                |                 |                 |                             |

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

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