Commit c61b0b97 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.7-2020-05-06' of... 

Merge tag 'amd-drm-fixes-5.7-2020-05-06' of git://people.freedesktop.org/~agd5f/linux

 into drm-fixes

amd-drm-fixes-5.7-2020-05-06:

amdgpu:
- Runtime PM fixes
- DC fix for PPC
- Misc DC fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506212257.3893-1-alexander.deucher@amd.com
parents 0e698dfa e6142dd5

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −5
Original line number Diff line number Diff line
@@ -3372,15 +3372,12 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 
		}

	}



	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);



	amdgpu_amdkfd_suspend(adev, !fbcon);



	amdgpu_ras_suspend(adev);



	r = amdgpu_device_ip_suspend_phase1(adev);



	amdgpu_amdkfd_suspend(adev, !fbcon);



	/* evict vram memory */

	amdgpu_bo_evict_vram(adev);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+11 −6
Original line number Diff line number Diff line
@@ -2008,17 +2008,22 @@ void amdgpu_dm_update_connector_after_detect( 
		dc_sink_retain(aconnector->dc_sink);

		if (sink->dc_edid.length == 0) {

			aconnector->edid = NULL;

			drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);

			if (aconnector->dc_link->aux_mode) {

				drm_dp_cec_unset_edid(

					&aconnector->dm_dp_aux.aux);

			}

		} else {

			aconnector->edid =

				(struct edid *)sink->dc_edid.raw_edid;





			drm_connector_update_edid_property(connector,

							   aconnector->edid);



			if (aconnector->dc_link->aux_mode)

				drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,

						    aconnector->edid);

		}



		amdgpu_dm_update_freesync_caps(connector, aconnector->edid);

		update_connector_ext_caps(aconnector);

	} else {

drivers/gpu/drm/amd/display/dc/core/dc.c

+2 −3
Original line number Diff line number Diff line
@@ -834,11 +834,10 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 
static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)

{

	int i;

	int count = 0;

	struct pipe_ctx *pipe;

	PERF_TRACE();

	for (i = 0; i < MAX_PIPES; i++) {

		pipe = &context->res_ctx.pipe_ctx[i];

		int count = 0;

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (!pipe->plane_state)

			continue;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+23 −8
Original line number Diff line number Diff line
@@ -3068,25 +3068,32 @@ validate_out: 
	return out;

}





bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

/*

 * This must be noinline to ensure anything that deals with FP registers

 * is contained within this call; previously our compiling with hard-float

 * would result in fp instructions being emitted outside of the boundaries

 * of the DC_FP_START/END macros, which makes sense as the compiler has no

 * idea about what is wrapped and what is not

 *

 * This is largely just a workaround to avoid breakage introduced with 5.6,

 * ideally all fp-using code should be moved into its own file, only that

 * should be compiled with hard-float, and all code exported from there

 * should be strictly wrapped with DC_FP_START/END

 */

static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,

		struct dc_state *context, bool fast_validate)

{

	bool voltage_supported = false;

	bool full_pstate_supported = false;

	bool dummy_pstate_supported = false;

	double p_state_latency_us;



	DC_FP_START();

	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =

		dc->debug.disable_dram_clock_change_vactive_support;



	if (fast_validate) {

		voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);



		DC_FP_END();

		return voltage_supported;

		return dcn20_validate_bandwidth_internal(dc, context, true);

	}



	// Best case, we support full UCLK switch latency
@@ -3115,7 +3122,15 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 


restore_dml_state:

	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;

	return voltage_supported;

}



bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

{

	bool voltage_supported = false;

	DC_FP_START();

	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);

	DC_FP_END();

	return voltage_supported;

}

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

+4 −4
Original line number Diff line number Diff line
@@ -1200,7 +1200,7 @@ static void dml_rq_dlg_get_dlg_params( 
	min_hratio_fact_l = 1.0;

	min_hratio_fact_c = 1.0;



	if (htaps_l <= 1)

	if (hratio_l <= 1)

		min_hratio_fact_l = 2.0;

	else if (htaps_l <= 6) {

		if ((hratio_l * 2.0) > 4.0)
@@ -1216,7 +1216,7 @@ static void dml_rq_dlg_get_dlg_params( 


	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;



	if (htaps_c <= 1)

	if (hratio_c <= 1)

		min_hratio_fact_c = 2.0;

	else if (htaps_c <= 6) {

		if ((hratio_c * 2.0) > 4.0)
@@ -1522,8 +1522,8 @@ static void dml_rq_dlg_get_dlg_params( 


	disp_dlg_regs->refcyc_per_vm_group_vblank   = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;

	disp_dlg_regs->refcyc_per_vm_group_flip     = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;

	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;

	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;

	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);

	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);



	// Clamp to max for now

	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

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