Unverified Commit c5e7fca9 authored by Kai Chieh Chuang's avatar Kai Chieh Chuang Committed by Mark Brown
Browse files

ASoC: mt6797: add structure define and clock control function for 6797 



Signed-off-by: default avatarKaiChieh Chuang <kaichieh.chuang@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f0ab0bf2

sound/soc/mediatek/mt6797/mt6797-afe-clk.c

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/*

 * mt6797-afe-clk.c  --  Mediatek 6797 afe clock ctrl

 *

 * Copyright (c) 2018 MediaTek Inc.

 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk.h>



#include "mt6797-afe-common.h"

#include "mt6797-afe-clk.h"



enum {

	CLK_INFRA_SYS_AUD,

	CLK_INFRA_SYS_AUD_26M,

	CLK_TOP_MUX_AUD,

	CLK_TOP_MUX_AUD_BUS,

	CLK_TOP_SYSPLL3_D4,

	CLK_TOP_SYSPLL1_D4,

	CLK_CLK26M,

	CLK_NUM

};



static const char *aud_clks[CLK_NUM] = {

	[CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",

	[CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",

	[CLK_TOP_MUX_AUD] = "top_mux_audio",

	[CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",

	[CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",

	[CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",

	[CLK_CLK26M] = "top_clk26m_clk",

};



int mt6797_init_clock(struct mtk_base_afe *afe)

{

	struct mt6797_afe_private *afe_priv = afe->platform_priv;

	int i;



	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),

				     GFP_KERNEL);

	if (!afe_priv->clk)

		return -ENOMEM;



	for (i = 0; i < CLK_NUM; i++) {

		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);

		if (IS_ERR(afe_priv->clk[i])) {

			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",

				__func__, aud_clks[i],

				PTR_ERR(afe_priv->clk[i]));

			return PTR_ERR(afe_priv->clk[i]);

		}

	}



	return 0;

}



int mt6797_afe_enable_clock(struct mtk_base_afe *afe)

{

	struct mt6797_afe_private *afe_priv = afe->platform_priv;

	int ret;



	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);

	if (ret) {

		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",

			__func__, aud_clks[CLK_INFRA_SYS_AUD], ret);

		goto CLK_INFRA_SYS_AUDIO_ERR;

	}



	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);

	if (ret) {

		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",

			__func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);

		goto CLK_INFRA_SYS_AUD_26M_ERR;

	}



	ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);

	if (ret) {

		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",

			__func__, aud_clks[CLK_TOP_MUX_AUD], ret);

		goto CLK_MUX_AUDIO_ERR;

	}



	ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],

			     afe_priv->clk[CLK_CLK26M]);

	if (ret) {

		dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",

			__func__, aud_clks[CLK_TOP_MUX_AUD],

			aud_clks[CLK_CLK26M], ret);

		goto CLK_MUX_AUDIO_ERR;

	}



	ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);

	if (ret) {

		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",

			__func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);

		goto CLK_MUX_AUDIO_INTBUS_ERR;

	}



	return ret;



CLK_MUX_AUDIO_INTBUS_ERR:

	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);

CLK_MUX_AUDIO_ERR:

	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);

CLK_INFRA_SYS_AUD_26M_ERR:

	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);

CLK_INFRA_SYS_AUDIO_ERR:

	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);



	return 0;

}



int mt6797_afe_disable_clock(struct mtk_base_afe *afe)

{

	struct mt6797_afe_private *afe_priv = afe->platform_priv;



	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);

	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);

	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);

	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);



	return 0;

}

sound/soc/mediatek/mt6797/mt6797-afe-clk.h

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/*

 * mt6797-afe-clk.h  --  Mediatek 6797 afe clock ctrl definition

 *

 * Copyright (c) 2018 MediaTek Inc.

 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _MT6797_AFE_CLK_H_

#define _MT6797_AFE_CLK_H_



struct mtk_base_afe;



int mt6797_init_clock(struct mtk_base_afe *afe);

int mt6797_afe_enable_clock(struct mtk_base_afe *afe);

int mt6797_afe_disable_clock(struct mtk_base_afe *afe);

#endif

sound/soc/mediatek/mt6797/mt6797-afe-common.h

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/*

 * mt6797-afe-common.h  --  Mediatek 6797 audio driver definitions

 *

 * Copyright (c) 2018 MediaTek Inc.

 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _MT_6797_AFE_COMMON_H_

#define _MT_6797_AFE_COMMON_H_



#include <sound/soc.h>

#include <linux/regmap.h>

#include "../common/mtk-base-afe.h"



enum {

	MT6797_MEMIF_DL1,

	MT6797_MEMIF_DL2,

	MT6797_MEMIF_DL3,

	MT6797_MEMIF_VUL,

	MT6797_MEMIF_AWB,

	MT6797_MEMIF_VUL12,

	MT6797_MEMIF_DAI,

	MT6797_MEMIF_MOD_DAI,

	MT6797_MEMIF_NUM,

	MT6797_DAI_ADDA = MT6797_MEMIF_NUM,

	MT6797_DAI_NUM,

};



enum {

	MT6797_IRQ_1,

	MT6797_IRQ_2,

	MT6797_IRQ_3,

	MT6797_IRQ_4,

	MT6797_IRQ_7,

	MT6797_IRQ_NUM,

};



struct clk;



struct mt6797_afe_private {

	struct clk **clk;

};



unsigned int mt6797_general_rate_transform(struct device *dev,

					   unsigned int rate);

unsigned int mt6797_rate_transform(struct device *dev,

				   unsigned int rate, int aud_blk);

#endif

sound/soc/mediatek/mt6797/mt6797-interconnection.h

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/*

 * Mediatek MT6797 audio driver interconnection definition

 *

 * Copyright (c) 2018 MediaTek Inc.

 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _MT6797_INTERCONNECTION_H_

#define _MT6797_INTERCONNECTION_H_



#define I_I2S0_CH1 0

#define I_I2S0_CH2 1

#define I_ADDA_UL_CH1 3

#define I_ADDA_UL_CH2 4

#define I_DL1_CH1 5

#define I_DL1_CH2 6

#define I_DL2_CH1 7

#define I_DL2_CH2 8

#define I_PCM_1_CAP_CH1 9

#define I_GAIN1_OUT_CH1 10

#define I_GAIN1_OUT_CH2 11

#define I_GAIN2_OUT_CH1 12

#define I_GAIN2_OUT_CH2 13

#define I_PCM_2_CAP_CH1 14

#define I_PCM_2_CAP_CH2 21

#define I_PCM_1_CAP_CH2 22

#define I_DL3_CH1 23

#define I_DL3_CH2 24

#define I_I2S2_CH1 25

#define I_I2S2_CH2 26



#endif

sound/soc/mediatek/mt6797/mt6797-reg.h

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