Commit c5e18af9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (27 commits)
  MIPS: Alchemy: time.c build fix
  MIPS: RB532: Export rb532_gpio_set_func()
  MIPS: RB532: Update headers
  MIPS: RB532: Simplify dev3 init
  MIPS: RB532: Remove {get,set}_434_reg()
  MIPS: RB532: Move dev3 init code to devices.c
  MIPS: RB532: Fix set_latch_u5()
  MIPS: RB532: Fix init of rb532_dev3_ctl_res
  MIPS: RB532: Use driver_data instead of platform_data
  MIPS: RB532: Detect uart type, add platform device
  MIPS: RB532: remove useless CF GPIO initialisation
  MIPS: RB532: Auto disable GPIO alternate function
  MIPS: RB532: Add set_type() function to IRQ struct.
  MIPS: RC32434: Define io_map_base for PCI controller
  MIPS: RB532: Fix bit swapping in rb532_set_bit()
  MIPS: Use hardware watchpoints on all R1 and R2 CPUs.
  MIPS: Read watch registers with interrupts disabled.
  MIPS: Fix a typo in watchpoint register structure.
  MIPS: TXx9: Add support for TX4939 internal RTC
  MIPS: R2: Fix broken installation of cache error handler.
  ...
parents 878b8619 2d2eca4d

arch/mips/Kconfig

+2 −5
Original line number Diff line number Diff line
@@ -351,7 +351,7 @@ config SGI_IP27 
	select ARC64

	select BOOT_ELF64

	select DEFAULT_SGI_PARTITION

	select DMA_IP27

	select DMA_COHERENT

	select SYS_HAS_EARLY_PRINTK

	select HW_HAS_PCI

	select NR_CPUS_DEFAULT_64
@@ -761,9 +761,6 @@ config CFE 
config DMA_COHERENT

	bool



config DMA_IP27

	bool



config DMA_NONCOHERENT

	bool

	select DMA_NEED_PCI_MAP_STATE
@@ -1368,7 +1365,7 @@ config CPU_SUPPORTS_64BIT_KERNEL 
#

config HARDWARE_WATCHPOINTS

       bool

       default y if CPU_MIPS32 || CPU_MIPS64

       default y if CPU_MIPSR1 || CPU_MIPSR2



menu "Kernel type"

arch/mips/alchemy/common/time.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { 
	.irq		= AU1000_RTC_MATCH2_INT,

	.set_next_event	= au1x_rtcmatch2_set_next_event,

	.set_mode	= au1x_rtcmatch2_set_mode,

	.cpumask	= CPU_MASK_ALL,

	.cpumask	= CPU_MASK_ALL_PTR,

};



static struct irqaction au1x_rtcmatch2_irqaction = {

arch/mips/cavium-octeon/setup.c

+0 −2
Original line number Diff line number Diff line
@@ -15,13 +15,11 @@ 
#include <linux/serial.h>

#include <linux/types.h>

#include <linux/string.h>	/* for memset */

#include <linux/serial.h>

#include <linux/tty.h>

#include <linux/time.h>

#include <linux/platform_device.h>

#include <linux/serial_core.h>

#include <linux/serial_8250.h>

#include <linux/string.h>



#include <asm/processor.h>

#include <asm/reboot.h>

arch/mips/configs/ip27_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ CONFIG_GENERIC_TIME=y 
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y

CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y

CONFIG_ARC=y

CONFIG_DMA_IP27=y

CONFIG_DMA_COHERENT=y

CONFIG_EARLY_PRINTK=y

CONFIG_SYS_HAS_EARLY_PRINTK=y

# CONFIG_NO_IOPORT is not set

arch/mips/include/asm/atomic.h

+26 −26
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ 
static __inline__ void atomic_add(int i, atomic_t * v)

{

	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) 
		: "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter));

	} else if (cpu_has_llsc) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) 
static __inline__ void atomic_sub(int i, atomic_t * v)

{

	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) 
		: "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter));

	} else if (cpu_has_llsc) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v) 
 */

static __inline__ int atomic_add_return(int i, atomic_t * v)

{

	unsigned long result;

	int result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) 


static __inline__ int atomic_sub_return(int i, atomic_t * v)

{

	unsigned long result;

	int result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) 
 */

static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)

{

	unsigned long result;

	int result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		int temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) 
static __inline__ void atomic64_add(long i, atomic64_t * v)

{

	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) 
		: "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter));

	} else if (cpu_has_llsc) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) 
static __inline__ void atomic64_sub(long i, atomic64_t * v)

{

	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) 
		: "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter));

	} else if (cpu_has_llsc) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) 
 */

static __inline__ long atomic64_add_return(long i, atomic64_t * v)

{

	unsigned long result;

	long result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 


static __inline__ long atomic64_sub_return(long i, atomic64_t * v)

{

	unsigned long result;

	long result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
 */

static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)

{

	unsigned long result;

	long result;



	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"
@@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 
		: "Ir" (i), "m" (v->counter)

		: "memory");

	} else if (cpu_has_llsc) {

		unsigned long temp;

		long temp;



		__asm__ __volatile__(

		"	.set	mips3					\n"

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