Commit c5e1503f authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: Fix execution hazard during watchpoint register probe 



Writing a value to a WatchLo* register creates an execution hazard, so
if its value is then read before that hazard is cleared then said value
may be invalid. The mips_probe_watch_registers function must therefore
clear the execution hazard between setting the match bits in a WatchLo*
register & reading the register back in order to check which are set.

This fixes intermittent incorrect watchpoint register probing on some
MIPS cores such as interAptiv & proAptiv.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/5474/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c37441c1

arch/mips/kernel/watch.c

+8 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 
	 * disable the register.

	 */

	write_c0_watchlo0(7);

	back_to_back_c0_hazard();

	t = read_c0_watchlo0();

	write_c0_watchlo0(0);

	c->watch_reg_masks[0] = t & 7;
@@ -121,12 +122,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 
	c->watch_reg_use_cnt = 1;

	t = read_c0_watchhi0();

	write_c0_watchhi0(t | 0xff8);

	back_to_back_c0_hazard();

	t = read_c0_watchhi0();

	c->watch_reg_masks[0] |= (t & 0xff8);

	if ((t & 0x80000000) == 0)

		return;



	write_c0_watchlo1(7);

	back_to_back_c0_hazard();

	t = read_c0_watchlo1();

	write_c0_watchlo1(0);

	c->watch_reg_masks[1] = t & 7;
@@ -135,12 +138,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 
	c->watch_reg_use_cnt = 2;

	t = read_c0_watchhi1();

	write_c0_watchhi1(t | 0xff8);

	back_to_back_c0_hazard();

	t = read_c0_watchhi1();

	c->watch_reg_masks[1] |= (t & 0xff8);

	if ((t & 0x80000000) == 0)

		return;



	write_c0_watchlo2(7);

	back_to_back_c0_hazard();

	t = read_c0_watchlo2();

	write_c0_watchlo2(0);

	c->watch_reg_masks[2] = t & 7;
@@ -149,12 +154,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 
	c->watch_reg_use_cnt = 3;

	t = read_c0_watchhi2();

	write_c0_watchhi2(t | 0xff8);

	back_to_back_c0_hazard();

	t = read_c0_watchhi2();

	c->watch_reg_masks[2] |= (t & 0xff8);

	if ((t & 0x80000000) == 0)

		return;



	write_c0_watchlo3(7);

	back_to_back_c0_hazard();

	t = read_c0_watchlo3();

	write_c0_watchlo3(0);

	c->watch_reg_masks[3] = t & 7;
@@ -163,6 +170,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 
	c->watch_reg_use_cnt = 4;

	t = read_c0_watchhi3();

	write_c0_watchhi3(t | 0xff8);

	back_to_back_c0_hazard();

	t = read_c0_watchhi3();

	c->watch_reg_masks[3] |= (t & 0xff8);

	if ((t & 0x80000000) == 0)

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