Commit c5e07e00 authored Sep 21, 2020 by Karthik B S Committed by Ville Syrjälä Sep 28, 2020

drm/i915: Add support for async flips in I915



Set the Async Address Update Enable bit in plane ctl
when async flip is requested.

v2: -Move the Async flip enablement to individual patch (Paulo)

v3: -Rebased.

v4: -Add separate plane hook for async flip case (Ville)

v5: -Rebased.

v6: -Move the plane hook to separate patch. (Paulo)
    -Remove the early return in skl_plane_ctl. (Paulo)

v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)

v8: -Rebased.

v9: -Rebased.

v10: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-3-karthik.b.s@intel.com

parent 1288f9b0

drivers/gpu/drm/i915/display/intel_display.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
		struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
		u32 plane_ctl = 0;

		if (crtc_state->uapi.async_flip)
		plane_ctl \|= PLANE_CTL_ASYNC_FLIP;

		if (INTEL_GEN(dev_priv) >= 10 \|\| IS_GEMINILAKE(dev_priv))
		return plane_ctl;

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -6923,6 +6923,7 @@ enum {
		#define PLANE_CTL_TILED_X (1 << 10)
		#define PLANE_CTL_TILED_Y (4 << 10)
		#define PLANE_CTL_TILED_YF (5 << 10)
		#define PLANE_CTL_ASYNC_FLIP (1 << 9)
		#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
		#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
		#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */

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