Merge tag 'mmc-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc (c5d6c138) · Commits · 戴 / test

Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Amlogic Meson SDHC controller Device Tree Bindings

		allOf:
		- $ref: "mmc-controller.yaml"

		maintainers:
		- Martin Blumenstingl <martin.blumenstingl@googlemail.com>

		description: \|
		The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
		card interface with 1/4/8-bit bus width.
		It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).

		properties:
		compatible:
		items:
		- enum:
		- amlogic,meson8-sdhc
		- amlogic,meson8b-sdhc
		- amlogic,meson8m2-sdhc
		- const: amlogic,meson-mx-sdhc

		reg:
		minItems: 1

		interrupts:
		minItems: 1

		clocks:
		minItems: 5

		clock-names:
		items:
		- const: clkin0
		- const: clkin1
		- const: clkin2
		- const: clkin3
		- const: pclk

		required:
		- compatible
		- reg
		- interrupts
		- clocks
		- clock-names

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/irq.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>

		sdhc: mmc@8e00 {
		compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
		reg = <0x8e00 0x42>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
		clocks = <&xtal>,
		<&fclk_div4>,
		<&fclk_div3>,
		<&fclk_div5>,
		<&sdhc_pclk>;
		clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
		};

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

+57 −0

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		@@ -18,12 +18,21 @@ Required Properties:
		- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
		For this device it is strongly suggested to include clock-output-names and
		#clock-cells.
		- "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
		For this device it is strongly suggested to include clock-output-names and
		#clock-cells.
		- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
		Note: This binding has been deprecated and moved to [5].
		- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		- "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		- "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		- "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.

		[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt

		@@ -104,6 +113,18 @@ Example:
		clk-phase-sd-hs = <63>, <72>;
		};

		sdhci: mmc@f1040000 {
		compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
		interrupt-parent = <&gic>;
		interrupts = <0 126 4>;
		reg = <0x0 0xf1040000 0x0 0x10000>;
		clocks = <&clk200>, <&clk200>;
		clock-names = "clk_xin", "clk_ahb";
		clock-output-names = "clk_out_sd0", "clk_in_sd0";
		#clock-cells = <1>;
		clk-phase-sd-hs = <132>, <60>;
		};

		emmc: sdhci@ec700000 {
		compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
		reg = <0xec700000 0x300>;
		@@ -133,3 +154,39 @@ Example:
		phy-names = "phy_arasan";
		arasan,soc-ctl-syscon = <&sysconf>;
		};

		mmc: mmc@33000000 {
		compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x33000000 0x0 0x300>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
		<&scmi_clk KEEM_BAY_PSS_EMMC>;
		phys = <&emmc_phy>;
		phy-names = "phy_arasan";
		assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
		assigned-clock-rates = <200000000>;
		clock-output-names = "emmc_cardclock";
		#clock-cells = <0>;
		arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
		};

		sd0: mmc@31000000 {
		compatible = "intel,keembay-sdhci-5.1-sd";
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x31000000 0x0 0x300>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
		<&scmi_clk KEEM_BAY_PSS_SD0>;
		arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
		};

		sd1: mmc@32000000 {
		compatible = "intel,keembay-sdhci-5.1-sdio";
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x32000000 0x0 0x300>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
		<&scmi_clk KEEM_BAY_PSS_SD1>;
		arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
		};

Documentation/devicetree/bindings/mmc/renesas,mmcif.txt

+3 −2

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@ Required properties:
		- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
		- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
		- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
		- "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
		- "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
		- "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
		- "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
		@@ -24,8 +25,8 @@ Required properties:
		- interrupts: Some SoCs have only 1 shared interrupt, while others have either
		2 or 3 individual interrupts (error, int, card detect). Below is the number
		of interrupts for each SoC:
		1: r8a73a4, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793,
		r8a7794
		1: r8a73a4, r8a7742, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791,
		r8a7793, r8a7794
		2: r8a7740, sh73a0
		3: r7s72100

Documentation/devicetree/bindings/mmc/renesas,sdhi.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@ Required properties:
		"renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
		"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
		"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
		"renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
		"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
		"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
		"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC

Documentation/devicetree/bindings/mmc/sdhci-msm.txt

+14 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,7 @@ Required properties:
		"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
		"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
		"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
		"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
		"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
		@@ -46,6 +47,13 @@ Required properties:
		"cal" - reference clock for RCLK delay calibration (optional)
		"sleep" - sleep clock for RCLK delay calibration (optional)

		- qcom,ddr-config: Certain chipsets and platforms require particular settings
		for the DDR_CONFIG register. Use this field to specify the register
		value as per the Hardware Programming Guide.

		- qcom,dll-config: Chipset and Platform specific value. Use this field to
		specify the DLL_CONFIG register value as per Hardware Programming Guide.

		Example:

		sdhc_1: sdhci@f9824900 {
		@@ -63,6 +71,9 @@ Example:

		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
		clock-names = "core", "iface";

		qcom,dll-config = <0x000f642c>;
		qcom,ddr-config = <0x80040868>;
		};

		sdhc_2: sdhci@f98a4900 {
		@@ -80,4 +91,7 @@ Example:

		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
		clock-names = "core", "iface";

		qcom,dll-config = <0x0007642c>;
		qcom,ddr-config = <0x80040868>;
		};

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