Commit c5cc2a0b authored by Tero Kristo's avatar Tero Kristo Committed by Stephen Boyd
Browse files

clk: ti: dpll: add support for specifying max rate for DPLLs 



DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Reviewed-by: default avatarNishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent fefe0535

drivers/clk/ti/clkt_dpll.c

+3 −0
Original line number Diff line number Diff line
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 


	dd = clk->dpll_data;



	if (dd->max_rate && target_rate > dd->max_rate)

		target_rate = dd->max_rate;



	ref_rate = clk_hw_get_rate(dd->clk_ref);

	clk_name = clk_hw_get_name(hw);

	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",

include/linux/clk/ti.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()

 * @min_divider: minimum valid non-bypass divider value (actual)

 * @max_divider: maximum valid non-bypass divider value (actual)

 * @max_rate: maximum clock rate for the DPLL

 * @modes: possible values of @enable_mask

 * @autoidle_reg: register containing the DPLL autoidle mode bitfield

 * @idlest_reg: register containing the DPLL idle status bitfield
@@ -81,6 +82,7 @@ struct dpll_data { 
	u8			last_rounded_n;

	u8			min_divider;

	u16			max_divider;

	unsigned long		max_rate;

	u8			modes;

	void __iomem		*autoidle_reg;

	void __iomem		*idlest_reg;

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