Commit c5aec4c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc updates from Ben Herrenschmidt:
 "Here is the bulk of the powerpc changes for this merge window.  It got
  a bit delayed in part because I wasn't paying attention, and in part
  because I discovered I had a core PCI change without a PCI maintainer
  ack in it.  Bjorn eventually agreed it was ok to merge it though we'll
  probably improve it later and I didn't want to rebase to add his ack.

  There is going to be a bit more next week, essentially fixes that I
  still want to sort through and test.

  The biggest item this time is the support to build the ppc64 LE kernel
  with our new v2 ABI.  We previously supported v2 userspace but the
  kernel itself was a tougher nut to crack.  This is now sorted mostly
  thanks to Anton and Rusty.

  We also have a fairly big series from Cedric that add support for
  64-bit LE zImage boot wrapper.  This was made harder by the fact that
  traditionally our zImage wrapper was always 32-bit, but our new LE
  toolchains don't really support 32-bit anymore (it's somewhat there
  but not really "supported") so we didn't want to rely on it.  This
  meant more churn that just endian fixes.

  This brings some more LE bits as well, such as the ability to run in
  LE mode without a hypervisor (ie. under OPAL firmware) by doing the
  right OPAL call to reinitialize the CPU to take HV interrupts in the
  right mode and the usual pile of endian fixes.

  There's another series from Gavin adding EEH improvements (one day we
  *will* have a release with less than 20 EEH patches, I promise!).

  Another highlight is the support for the "Split core" functionality on
  P8 by Michael.  This allows a P8 core to be split into "sub cores" of
  4 threads which allows the subcores to run different guests under KVM
  (the HW still doesn't support a partition per thread).

  And then the usual misc bits and fixes ..."

[ Further delayed by gmail deciding that BenH is a dirty spammer.
  Google knows.  ]

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits)
  powerpc/powernv: Add missing include to LPC code
  selftests/powerpc: Test the THP bug we fixed in the previous commit
  powerpc/mm: Check paca psize is up to date for huge mappings
  powerpc/powernv: Pass buffer size to OPAL validate flash call
  powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC()
  powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC()
  powerpc/powernv: Set memory_block_size_bytes to 256MB
  powerpc: Allow ppc_md platform hook to override memory_block_size_bytes
  powerpc/powernv: Fix endian issues in memory error handling code
  powerpc/eeh: Skip eeh sysfs when eeh is disabled
  powerpc: 64bit sendfile is capped at 2GB
  powerpc/powernv: Provide debugfs access to the LPC bus via OPAL
  powerpc/serial: Use saner flags when creating legacy ports
  powerpc: Add cpu family documentation
  powerpc/xmon: Fix up xmon format strings
  powerpc/powernv: Add calls to support little endian host
  powerpc: Document sysfs DSCR interface
  powerpc: Fix regression of per-CPU DSCR setting
  powerpc: Split __SYSFS_SPRSETUP macro
  arch: powerpc/fadump: Cleaning up inconsistent NULL checks
  ...
parents 2937f5ef 0c0a3e5a

Documentation/ABI/stable/sysfs-devices-system-cpu

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What: 		/sys/devices/system/cpu/dscr_default

Date:		13-May-2014

KernelVersion:	v3.15.0

Contact:

Description:	Writes are equivalent to writing to

		/sys/devices/system/cpu/cpuN/dscr on all CPUs.

		Reads return the last written value or 0.

		This value is not a global default: it is a way to set

		all per-CPU defaults at the same time.

Values:		64 bit unsigned integer (bit field)



What: 		/sys/devices/system/cpu/cpu[0-9]+/dscr

Date:		13-May-2014

KernelVersion:	v3.15.0

Contact:

Description:	Default value for the Data Stream Control Register (DSCR) on

		a CPU.

		This default value is used when the kernel is executing and

		for any process that has not set the DSCR itself.

		If a process ever sets the DSCR (via direct access to the

		SPR) that value will be persisted for that process and used

		on any CPU where it executes (overriding the value described

		here).

		If set by a process it will be inherited by child processes.

Values:		64 bit unsigned integer (bit field)

Documentation/devicetree/bindings/clock/corenet-clock.txt→Documentation/devicetree/bindings/clock/qoriq-clock.txt

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@@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including 
cores and peripheral IP blocks.

Please refer to the Reference Manual for details.



All references to "1.0" and "2.0" refer to the QorIQ chassis version to

which the chip complies.



Chassis Version		Example Chips

---------------		-------------

1.0			p4080, p5020, p5040

2.0			t4240, b4860, t1040



1. Clock Block Binding



Required properties:
@@ -85,7 +93,7 @@ Example for clock block and clock provider: 
			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		}

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

Documentation/devicetree/bindings/mfd/bfticu.txt

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KEYMILE bfticu Chassis Management FPGA



The bfticu is a multifunction device that manages the whole chassis.

Its main functionality is to collect IRQs from the whole chassis and signals

them to a single controller.



Required properties:

- compatible: "keymile,bfticu"

- interrupt-controller: the bfticu FPGA is an interrupt controller

- interrupts: the main IRQ line to signal the collected IRQs

- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant

  of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to

- reg: access on the parent local bus (chip select, offset in chip select, size)



Example:



	chassis-mgmt@3,0 {

		compatible = "keymile,bfticu";

		interrupt-controller;

		#interrupt-cells = <2>;

		reg = <3 0 0x100>;

		interrupt-parent = <&mpic>;

		interrupts = <6 1 0 0>;

	};

Documentation/devicetree/bindings/mfd/qriox.txt

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KEYMILE qrio Board Control CPLD



The qrio is a multifunction device that controls the KEYMILE boards based on

the kmp204x design.

It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable

GPIO blocks.



Required properties:

- compatible: "keymile,qriox"

- reg: access on the parent local bus (chip select, offset in chip select, size)



Example:



	board-control@1,0 {

		compatible = "keymile,qriox";

		reg = <1 0 0x80>;

	};

Documentation/devicetree/bindings/powerpc/4xx/akebono.txt

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IBM Akebono board device tree

=============================



The IBM Akebono board is a development board for the PPC476GTR SoC.



0) The root node



   Required properties:



   - model : "ibm,akebono".

   - compatible : "ibm,akebono" , "ibm,476gtr".



1.a) The Secure Digital Host Controller Interface (SDHCI) node



  Represent the Secure Digital Host Controller Interfaces.



  Required properties:



   - compatible : should be "ibm,476gtr-sdhci","generic-sdhci".

   - reg : should contain the SDHCI registers location and length.

   - interrupt-parent : a phandle for the interrupt controller.

   - interrupts : should contain the SDHCI interrupt.



1.b) The Advanced Host Controller Interface (AHCI) SATA node



  Represents the advanced host controller SATA interface.



  Required properties:



   - compatible : should be "ibm,476gtr-ahci".

   - reg : should contain the AHCI registers location and length.

   - interrupt-parent : a phandle for the interrupt controller.

   - interrupts : should contain the AHCI interrupt.



1.c) The FPGA node



  The Akebono board stores some board information such as the revision

  number in an FPGA which is represented by this node.



  Required properties:



   - compatible : should be "ibm,akebono-fpga".

   - reg : should contain the FPGA registers location and length.



1.d) The AVR node



  The Akebono board has an Atmel AVR microprocessor attached to the I2C

  bus as a power controller for the board.



  Required properties:



   - compatible : should be "ibm,akebono-avr".

   - reg : should contain the I2C bus address for the AVR.

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