Commit c59d2da8 authored Sep 10, 2018 by P Raviraj Sitaram Committed by Ville Syrjälä Sep 11, 2018

drm/i915/chv: Update csc coefficient matrix during modeset



During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.

Changes since V1:
- Removed platform check

Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1536589634-29680-1-git-send-email-raviraj.p.sitaram@intel.com

parent b84d9ab0

drivers/gpu/drm/i915/intel_display.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -6013,6 +6013,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,

		i9xx_set_pipeconf(intel_crtc);

		intel_color_set_csc(&pipe_config->base);

		intel_crtc->active = true;

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

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