Commit c535bfdd authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs: use EQ MSI/X ID per chip



The Event Queue MSI/X ID is different per ASIC. This patch renames the
current define to have the GOYA_ prefix to mark it only for Goya. It also
moves it from the common armcp_if.h file to the ASIC specific goya_fw_if.h
file.

Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 3110c60f
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+4 −4
Original line number Diff line number Diff line
@@ -2204,10 +2204,10 @@ static int goya_enable_msix(struct hl_device *hdev)
		}
	}

	irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
	irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);

	rc = request_irq(irq, hl_irq_handler_eq, 0,
			goya_irq_name[EVENT_QUEUE_MSIX_IDX],
			goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
			&hdev->event_queue);
	if (rc) {
		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
@@ -2238,7 +2238,7 @@ static void goya_sync_irqs(struct hl_device *hdev)
	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
		synchronize_irq(pci_irq_vector(hdev->pdev, i));

	synchronize_irq(pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX));
	synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
}

static void goya_disable_msix(struct hl_device *hdev)
@@ -2251,7 +2251,7 @@ static void goya_disable_msix(struct hl_device *hdev)

	goya_sync_irqs(hdev);

	irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
	irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
	free_irq(irq, &hdev->event_queue);

	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
+0 −2
Original line number Diff line number Diff line
@@ -32,8 +32,6 @@ struct hl_eq_entry {
#define EQ_CTL_EVENT_TYPE_SHIFT		16
#define EQ_CTL_EVENT_TYPE_MASK		0x03FF0000

#define EVENT_QUEUE_MSIX_IDX		5

enum pq_init_status {
	PQ_INIT_STATUS_NA = 0,
	PQ_INIT_STATUS_READY_FOR_CP,
+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@
#ifndef GOYA_FW_IF_H
#define GOYA_FW_IF_H

#define GOYA_EVENT_QUEUE_MSIX_IDX	5

#define CPU_BOOT_ADDR		0x7FF8040000ull

#define UBOOT_FW_OFFSET		0x100000		/* 1MB in SRAM */