Commit c50fe0c5 authored by Aaron Liu's avatar Aaron Liu Committed by Alex Deucher
Browse files

drm/amdgpu: both support PCO FP5/AM4 rlc fw 



For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
For Picasso && FP5 SOCKET board, we use picasso_rlc.bin

Judgment method:
PCO AM4: revision >= 0xC8 && revision <= 0xCF
         or revision >= 0xD8 && revision <= 0xDF
otherwise is PCO FP5

Signed-off-by: default avatarAaron Liu <aaron.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 34c08da2

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+15 −1
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 
MODULE_FIRMWARE("amdgpu/picasso_mec.bin");

MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");

MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");

MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");



MODULE_FIRMWARE("amdgpu/raven2_ce.bin");

MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
@@ -645,6 +646,19 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	/*

	 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin

	 * instead of picasso_rlc.bin.

	 * Judgment method:

	 * PCO AM4: revision >= 0xC8 && revision <= 0xCF

	 *          or revision >= 0xD8 && revision <= 0xDF

	 * otherwise is PCO FP5

	 */

	if (!strcmp(chip_name, "picasso") &&

		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||

		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);

	else

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);

	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);

	if (err)

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