Commit c50dfe79 authored Jul 25, 2018 by Paulo Zanoni

drm/i915/icl: don't set CNL_DDI_CLOCK_REG_ACCESS_ON anymore



The new recommendation from the spec is to simply not set this bit
anymore. Not setting the bit would prevent some hangs that our driver
manages to avoid since commit c8af5274 ("drm/i915: enable the
pipe/transcoder/planes later on HSW+"), and the theoretical downside
of not setting the bit doesn't seem realistic according to the HW
team. Let's follow their recommendation.

BSpec: 20233
References: commit c8af5274 ("drm/i915: enable the
 pipe/transcoder/planes later on HSW+")
Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180726001229.13791-1-paulo.r.zanoni@intel.com

parent 5503cb0d

drivers/gpu/drm/i915/intel_runtime_pm.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -3372,10 +3372,6 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,

		/* 7. Setup MBUS. */
		icl_mbus_init(dev_priv);

		/* 8. CHICKEN_DCPR_1 */
		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) \|
		CNL_DDI_CLOCK_REG_ACCESS_ON);
		}

		static void icl_display_core_uninit(struct drm_i915_private *dev_priv)

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