Commit c4f16e96 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
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memory: samsung: exynos5422-dmc: Do not ignore return code of regmap_read() 



Check for regmap_read() return code before using the read value in
following write in exynos5_switch_timing_regs().  Pass reading error
code to the callers.

This does not introduce proper error handling for such failed reads (and
obviously regmap_write() error is still ignored) because the driver
ignored this in all places.  Therefor it only fixes reported issue while
matching current driver coding style:

       drivers/memory/samsung/exynos5422-dmc.c: In function 'exynos5_switch_timing_regs':
    >> drivers/memory/samsung/exynos5422-dmc.c:216:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]

Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent b3a9e3b9

drivers/memory/samsung/exynos5422-dmc.c

+9 −3
Original line number Diff line number Diff line
@@ -270,12 +270,14 @@ static int find_target_freq_idx(struct exynos5_dmc *dmc, 
 * This function switches between these banks according to the

 * currently used clock source.

 */

static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)

static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)

{

	unsigned int reg;

	int ret;



	ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg);

	if (ret)

		return ret;



	if (set)

		reg |= EXYNOS5_TIMING_SET_SWI;
@@ -283,6 +285,8 @@ static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) 
		reg &= ~EXYNOS5_TIMING_SET_SWI;



	regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);



	return 0;

}



/**
@@ -516,7 +520,7 @@ exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, 
	/*

	 * Delays are long enough, so use them for the new coming clock.

	 */

	exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);

	ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);



	return ret;

}
@@ -577,7 +581,9 @@ exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, 


	clk_set_rate(dmc->fout_bpll, target_rate);



	exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);

	ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);

	if (ret)

		goto disable_clocks;



	ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);

	if (ret)

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