Unverified Commit c4eadee2 authored by Wan Ahmad Zainie's avatar Wan Ahmad Zainie Committed by Mark Brown
Browse files

spi: dw: Add update_cr0() callback to update CTRLR0 



This patch adds update_cr0() callback, in struct dw_spi.

Existing code that configure register CTRLR0 is moved into a new
function, dw_spi_update_cr0(), and this will be the default.

Suggested-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarWan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200505130618.554-3-wan.ahmad.zainie.wan.mohamad@intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 299cb65c

drivers/spi/spi-dw-mid.c

+4 −0
Original line number Diff line number Diff line
@@ -318,5 +318,9 @@ int dw_spi_mid_init(struct dw_spi *dws) 
	dws->dma_rx = &mid_dma_rx;

	dws->dma_ops = &mid_dma_ops;

#endif



	/* Register hook to configure CTRLR0 */

	dws->update_cr0 = dw_spi_update_cr0;



	return 0;

}

drivers/spi/spi-dw-mmio.c

+18 −3
Original line number Diff line number Diff line
@@ -106,6 +106,9 @@ static int dw_spi_mscc_init(struct platform_device *pdev, 
	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;

	dwsmmio->priv = dwsmscc;



	/* Register hook to configure CTRLR0 */

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;



	return 0;

}
@@ -128,6 +131,18 @@ static int dw_spi_alpine_init(struct platform_device *pdev, 
{

	dwsmmio->dws.cs_override = 1;



	/* Register hook to configure CTRLR0 */

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;



	return 0;

}



static int dw_spi_dw_apb_init(struct platform_device *pdev,

			      struct dw_spi_mmio *dwsmmio)

{

	/* Register hook to configure CTRLR0 */

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;



	return 0;

}
@@ -224,17 +239,17 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) 
}



static const struct of_device_id dw_spi_mmio_of_match[] = {

	{ .compatible = "snps,dw-apb-ssi", },

	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},

	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},

	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},

	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},

	{ .compatible = "renesas,rzn1-spi", },

	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},

	{ /* end of table */}

};

MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);



static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {

	{"HISI0173", 0},

	{"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},

	{},

};

MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);

drivers/spi/spi-dw.c

+21 −8
Original line number Diff line number Diff line
@@ -257,6 +257,26 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) 
	return dws->transfer_handler(dws);

}



/* Configure CTRLR0 for DW_apb_ssi */

u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi,

		      struct spi_transfer *transfer)

{

	struct dw_spi *dws = spi_controller_get_devdata(master);

	struct chip_data *chip = spi_get_ctldata(spi);

	u32 cr0;



	/* Default SPI mode is SCPOL = 0, SCPH = 0 */

	cr0 = (transfer->bits_per_word - 1)

		| (chip->type << SPI_FRF_OFFSET)

		| ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |

		   (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |

		   (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))

		| (chip->tmode << SPI_TMOD_OFFSET);



	return cr0;

}

EXPORT_SYMBOL_GPL(dw_spi_update_cr0);



static int dw_spi_transfer_one(struct spi_controller *master,

		struct spi_device *spi, struct spi_transfer *transfer)

{
@@ -296,14 +316,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, 
	dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);

	dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);



	/* Default SPI mode is SCPOL = 0, SCPH = 0 */

	cr0 = (transfer->bits_per_word - 1)

		| (chip->type << SPI_FRF_OFFSET)

		| ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |

			(((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |

			(((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))

		| (chip->tmode << SPI_TMOD_OFFSET);



	cr0 = dws->update_cr0(master, spi, transfer);

	dw_writel(dws, DW_SPI_CTRLR0, cr0);



	/* Check if current transfer is a DMA transaction */

drivers/spi/spi-dw.h

+5 −0
Original line number Diff line number Diff line
@@ -114,6 +114,8 @@ struct dw_spi { 
	u16			bus_num;

	u16			num_cs;		/* supported slave numbers */

	void (*set_cs)(struct spi_device *spi, bool enable);

	u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi,

			  struct spi_transfer *transfer);



	/* Current message transfer state info */

	size_t			len;
@@ -240,6 +242,9 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 
extern void dw_spi_remove_host(struct dw_spi *dws);

extern int dw_spi_suspend_host(struct dw_spi *dws);

extern int dw_spi_resume_host(struct dw_spi *dws);

extern u32 dw_spi_update_cr0(struct spi_controller *master,

			     struct spi_device *spi,

			     struct spi_transfer *transfer);



/* platform related setup */

extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */

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