Merge branch 'acpi-soc' into pm-core (c4e4d631) · Commits · 戴 / test

arch/x86/Kconfig

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -523,9 +523,10 @@ config X86_INTEL_QUARK

	config X86_INTEL_LPSS		config X86_INTEL_LPSS
	bool "Intel Low Power Subsystem Support"		bool "Intel Low Power Subsystem Support"
	depends on ACPI		depends on X86 && ACPI
	select COMMON_CLK		select COMMON_CLK
	select PINCTRL		select PINCTRL
			select IOSF_MBI
	---help---		---help---
	Select to build support for Intel Low Power Subsystem such as		Select to build support for Intel Low Power Subsystem such as
	found on Intel Lynxpoint PCH. Selecting this option enables		found on Intel Lynxpoint PCH. Selecting this option enables

arch/x86/include/asm/iosf_mbi.h

+13 −38

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* iosf_mbi.h: Intel OnChip System Fabric MailBox access support		* Intel OnChip System Fabric MailBox access support
	*/		*/

	#ifndef IOSF_MBI_SYMS_H		#ifndef IOSF_MBI_SYMS_H
	@@ -16,6 +16,18 @@
	#define MBI_MASK_LO 0x000000FF		#define MBI_MASK_LO 0x000000FF
	#define MBI_ENABLE 0xF0		#define MBI_ENABLE 0xF0

			/* IOSF SB read/write opcodes */
			#define MBI_MMIO_READ 0x00
			#define MBI_MMIO_WRITE 0x01
			#define MBI_CFG_READ 0x04
			#define MBI_CFG_WRITE 0x05
			#define MBI_CR_READ 0x06
			#define MBI_CR_WRITE 0x07
			#define MBI_REG_READ 0x10
			#define MBI_REG_WRITE 0x11
			#define MBI_ESRAM_READ 0x12
			#define MBI_ESRAM_WRITE 0x13

	/* Baytrail available units */		/* Baytrail available units */
	#define BT_MBI_UNIT_AUNIT 0x00		#define BT_MBI_UNIT_AUNIT 0x00
	#define BT_MBI_UNIT_SMC 0x01		#define BT_MBI_UNIT_SMC 0x01
	@@ -28,50 +40,13 @@
	#define BT_MBI_UNIT_SATA 0xA3		#define BT_MBI_UNIT_SATA 0xA3
	#define BT_MBI_UNIT_PCIE 0xA6		#define BT_MBI_UNIT_PCIE 0xA6

	/* Baytrail read/write opcodes */
	#define BT_MBI_AUNIT_READ 0x10
	#define BT_MBI_AUNIT_WRITE 0x11
	#define BT_MBI_SMC_READ 0x10
	#define BT_MBI_SMC_WRITE 0x11
	#define BT_MBI_CPU_READ 0x10
	#define BT_MBI_CPU_WRITE 0x11
	#define BT_MBI_BUNIT_READ 0x10
	#define BT_MBI_BUNIT_WRITE 0x11
	#define BT_MBI_PMC_READ 0x06
	#define BT_MBI_PMC_WRITE 0x07
	#define BT_MBI_GFX_READ 0x00
	#define BT_MBI_GFX_WRITE 0x01
	#define BT_MBI_SMIO_READ 0x06
	#define BT_MBI_SMIO_WRITE 0x07
	#define BT_MBI_USB_READ 0x06
	#define BT_MBI_USB_WRITE 0x07
	#define BT_MBI_SATA_READ 0x00
	#define BT_MBI_SATA_WRITE 0x01
	#define BT_MBI_PCIE_READ 0x00
	#define BT_MBI_PCIE_WRITE 0x01

	/* Quark available units */		/* Quark available units */
	#define QRK_MBI_UNIT_HBA 0x00		#define QRK_MBI_UNIT_HBA 0x00
	#define QRK_MBI_UNIT_HB 0x03		#define QRK_MBI_UNIT_HB 0x03
	#define QRK_MBI_UNIT_RMU 0x04		#define QRK_MBI_UNIT_RMU 0x04
	#define QRK_MBI_UNIT_MM 0x05		#define QRK_MBI_UNIT_MM 0x05
	#define QRK_MBI_UNIT_MMESRAM 0x05
	#define QRK_MBI_UNIT_SOC 0x31		#define QRK_MBI_UNIT_SOC 0x31

	/* Quark read/write opcodes */
	#define QRK_MBI_HBA_READ 0x10
	#define QRK_MBI_HBA_WRITE 0x11
	#define QRK_MBI_HB_READ 0x10
	#define QRK_MBI_HB_WRITE 0x11
	#define QRK_MBI_RMU_READ 0x10
	#define QRK_MBI_RMU_WRITE 0x11
	#define QRK_MBI_MM_READ 0x10
	#define QRK_MBI_MM_WRITE 0x11
	#define QRK_MBI_MMESRAM_READ 0x12
	#define QRK_MBI_MMESRAM_WRITE 0x13
	#define QRK_MBI_SOC_READ 0x06
	#define QRK_MBI_SOC_WRITE 0x07

	#if IS_ENABLED(CONFIG_IOSF_MBI)		#if IS_ENABLED(CONFIG_IOSF_MBI)

	bool iosf_mbi_available(void);		bool iosf_mbi_available(void);

arch/x86/platform/atom/punit_atom_debug.c

+2 −5

Original line number	Original line	Diff line number	Diff line
	@@ -25,8 +25,6 @@
	#include <asm/cpu_device_id.h>		#include <asm/cpu_device_id.h>
	#include <asm/iosf_mbi.h>		#include <asm/iosf_mbi.h>

	/* Side band Interface port */
	#define PUNIT_PORT 0x04
	/* Power gate status reg */		/* Power gate status reg */
	#define PWRGT_STATUS 0x61		#define PWRGT_STATUS 0x61
	/* Subsystem config/status Video processor */		/* Subsystem config/status Video processor */
	@@ -85,9 +83,8 @@ static int punit_dev_state_show(struct seq_file seq_file, void unused)

	seq_puts(seq_file, "\n\nPUNIT NORTH COMPLEX DEVICES :\n");		seq_puts(seq_file, "\n\nPUNIT NORTH COMPLEX DEVICES :\n");
	while (punit_devp->name) {		while (punit_devp->name) {
	status = iosf_mbi_read(PUNIT_PORT, BT_MBI_PMC_READ,		status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
	punit_devp->reg,		punit_devp->reg, &punit_pwr_status);
	&punit_pwr_status);
	if (status) {		if (status) {
	seq_printf(seq_file, "%9s : Read Failed\n",		seq_printf(seq_file, "%9s : Read Failed\n",
	punit_devp->name);		punit_devp->name);

arch/x86/platform/intel-quark/imr.c

+10 −18

Original line number	Original line	Diff line number	Diff line
	@@ -111,23 +111,19 @@ static int imr_read(struct imr_device idev, u32 imr_id, struct imr_regs imr)
	u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base;		u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base;
	int ret;		int ret;

	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, QRK_MBI_MM_READ,		ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_lo);
	reg++, &imr->addr_lo);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, QRK_MBI_MM_READ,		ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_hi);
	reg++, &imr->addr_hi);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, QRK_MBI_MM_READ,		ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->rmask);
	reg++, &imr->rmask);
	if (ret)		if (ret)
	return ret;		return ret;

	return iosf_mbi_read(QRK_MBI_UNIT_MM, QRK_MBI_MM_READ,		return iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->wmask);
	reg++, &imr->wmask);
	}		}

	/**		/**
	@@ -151,30 +147,26 @@ static int imr_write(struct imr_device *idev, u32 imr_id,

	local_irq_save(flags);		local_irq_save(flags);

	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, QRK_MBI_MM_WRITE, reg++,		ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_lo);
	imr->addr_lo);
	if (ret)		if (ret)
	goto failed;		goto failed;

	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, QRK_MBI_MM_WRITE,		ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_hi);
	reg++, imr->addr_hi);
	if (ret)		if (ret)
	goto failed;		goto failed;

	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, QRK_MBI_MM_WRITE,		ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->rmask);
	reg++, imr->rmask);
	if (ret)		if (ret)
	goto failed;		goto failed;

	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, QRK_MBI_MM_WRITE,		ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->wmask);
	reg++, imr->wmask);
	if (ret)		if (ret)
	goto failed;		goto failed;

	/* Lock bit must be set separately to addr_lo address bits. */		/* Lock bit must be set separately to addr_lo address bits. */
	if (lock) {		if (lock) {
	imr->addr_lo \|= IMR_LOCK;		imr->addr_lo \|= IMR_LOCK;
	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, QRK_MBI_MM_WRITE,		ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE,
	reg - IMR_NUM_REGS, imr->addr_lo);		reg - IMR_NUM_REGS, imr->addr_lo);
	if (ret)		if (ret)
	goto failed;		goto failed;

drivers/acpi/acpi_apd.c

+15 −1

Original line number	Original line	Diff line number	Diff line
	@@ -51,7 +51,7 @@ struct apd_private_data {
	const struct apd_device_desc *dev_desc;		const struct apd_device_desc *dev_desc;
	};		};

	#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE		#if defined(CONFIG_X86_AMD_PLATFORM_DEVICE) \|\| defined(CONFIG_ARM64)
	#define APD_ADDR(desc) ((unsigned long)&desc)		#define APD_ADDR(desc) ((unsigned long)&desc)

	static int acpi_apd_setup(struct apd_private_data *pdata)		static int acpi_apd_setup(struct apd_private_data *pdata)
	@@ -71,6 +71,7 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
	return 0;		return 0;
	}		}

			#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
	static struct apd_device_desc cz_i2c_desc = {		static struct apd_device_desc cz_i2c_desc = {
	.setup = acpi_apd_setup,		.setup = acpi_apd_setup,
	.fixed_clk_rate = 133000000,		.fixed_clk_rate = 133000000,
	@@ -80,6 +81,14 @@ static struct apd_device_desc cz_uart_desc = {
	.setup = acpi_apd_setup,		.setup = acpi_apd_setup,
	.fixed_clk_rate = 48000000,		.fixed_clk_rate = 48000000,
	};		};
			#endif

			#ifdef CONFIG_ARM64
			static struct apd_device_desc xgene_i2c_desc = {
			.setup = acpi_apd_setup,
			.fixed_clk_rate = 100000000,
			};
			#endif

	#else		#else

	@@ -132,9 +141,14 @@ static int acpi_apd_create_device(struct acpi_device *adev,

	static const struct acpi_device_id acpi_apd_device_ids[] = {		static const struct acpi_device_id acpi_apd_device_ids[] = {
	/* Generic apd devices */		/* Generic apd devices */
			#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
	{ "AMD0010", APD_ADDR(cz_i2c_desc) },		{ "AMD0010", APD_ADDR(cz_i2c_desc) },
	{ "AMD0020", APD_ADDR(cz_uart_desc) },		{ "AMD0020", APD_ADDR(cz_uart_desc) },
	{ "AMD0030", },		{ "AMD0030", },
			#endif
			#ifdef CONFIG_ARM64
			{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
			#endif
	{ }		{ }
	};		};

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