Commit c4d7e58f authored by Paul Walmsley's avatar Paul Walmsley
Browse files

OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_" 



Now that OMAP4-specific PRCM functions have been added, distinguish the
existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_".

This patch should not result in any functional change.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
parent dac9a771

arch/arm/mach-omap2/clkt2xxx_apll.c

+5 −5
Original line number Diff line number Diff line
@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) 


	apll_mask = EN_APLL_LOCKED << clk->enable_bit;



	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);



	if ((cval & apll_mask) == apll_mask)

		return 0;   /* apll already enabled */



	cval &= ~apll_mask;

	cval |= apll_mask;

	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);



	omap2_cm_wait_idlest(cm_idlest_pll, status_mask,

			     OMAP24XX_CM_IDLEST_VAL, clk->name);
@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) 
{

	u32 cval;



	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);

	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

}



/* Public data */
@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) 
{

	u32 aplls, srate = 0;



	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);

	aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);

	aplls &= OMAP24XX_APLLS_CLKIN_MASK;

	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;

arch/arm/mach-omap2/clkt2xxx_dpllcore.c

+4 −4
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) 


	core_clk = omap2_get_dpll_rate(clk);



	v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	v &= OMAP24XX_CORE_CLK_SRC_MASK;



	if (v == CORE_CLK_SRC_32K)
@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) 
{

	u32 high, low, core_clk_src;



	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;



	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
	const struct dpll_data *dd;



	cur_rate = omap2xxx_clk_get_core_rate(dclk);

	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	mult &= OMAP24XX_CORE_CLK_SRC_MASK;



	if ((rate == (cur_rate / 2)) && (mult == 2)) {
@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |

					   dd->div1_mask);

		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);

		tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

		tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;

		if (rate > low) {

			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;

arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c

+6 −6
Original line number Diff line number Diff line
@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) 
			done_rate = CORE_CLK_SRC_DPLL;



		/* MPU divider */

		cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);

		omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);



		/* dsp + iva1 div(2420), iva2.1(2430) */

		cm_write_mod_reg(prcm->cm_clksel_dsp,

		omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,

				 OMAP24XX_DSP_MOD, CM_CLKSEL);



		cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);

		omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);



		/* Major subsystem dividers */

		tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;

		cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,

		tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;

		omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,

				 CM_CLKSEL1);



		if (cpu_is_omap2430())

			cm_write_mod_reg(prcm->cm_clksel_mdm,

			omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,

					 OMAP2430_MDM_MOD, CM_CLKSEL);



		/* x2 to enter omap2xxx_sdrc_init_params() */

arch/arm/mach-omap2/clockdomain.c

+10 −12
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 
 */

#undef DEBUG



#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/device.h>

#include <linux/list.h>
@@ -30,7 +29,6 @@ 
#include "prm2xxx_3xxx.h"

#include "prm-regbits-24xx.h"

#include "cm2xxx_3xxx.h"

#include "cm2xxx_3xxx.h"



#include <plat/clock.h>

#include <plat/powerdomain.h>
@@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
		pr_debug("clockdomain: hardware will wake up %s when %s wakes "

			 "up\n", clkdm1->name, clkdm2->name);



		prm_set_mod_reg_bits((1 << clkdm2->dep_bit),

		omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),

				     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);

	}
@@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
		pr_debug("clockdomain: hardware will no longer wake up %s "

			 "after %s wakes up\n", clkdm1->name, clkdm2->name);



		prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),

		omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),

				       clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);

	}
@@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
	}



	/* XXX It's faster to return the atomic wkdep_usecount */

	return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,

	return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,

				       (1 << clkdm2->dep_bit));

}
@@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) 
		atomic_set(&cd->wkdep_usecount, 0);

	}



	prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);

	omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);



	return 0;

}
@@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
		pr_debug("clockdomain: will prevent %s from sleeping if %s "

			 "is active\n", clkdm1->name, clkdm2->name);



		cm_set_mod_reg_bits((1 << clkdm2->dep_bit),

		omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),

				    clkdm1->pwrdm.ptr->prcm_offs,

				    OMAP3430_CM_SLEEPDEP);

	}
@@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
			 "sleeping if %s is active\n", clkdm1->name,

			 clkdm2->name);



		cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),

		omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),

				      clkdm1->pwrdm.ptr->prcm_offs,

				      OMAP3430_CM_SLEEPDEP);

	}
@@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 
	}



	/* XXX It's faster to return the atomic sleepdep_usecount */

	return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,

	return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,

				       OMAP3430_CM_SLEEPDEP,

				       (1 << clkdm2->dep_bit));

}
@@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) 
		atomic_set(&cd->sleepdep_usecount, 0);

	}



	prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,

	omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,

			       OMAP3430_CM_SLEEPDEP);



	return 0;
@@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) 


	if (cpu_is_omap24xx()) {



		cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

		omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

			    clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) 


	if (cpu_is_omap24xx()) {



		cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

		omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

			      clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {

arch/arm/mach-omap2/cm2xxx_3xxx.c

+181 −171
Original line number Diff line number Diff line
@@ -29,37 +29,37 @@ static const u8 cm_idlest_offs[] = { 
	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3

};



u32 cm_read_mod_reg(s16 module, u16 idx)

u32 omap2_cm_read_mod_reg(s16 module, u16 idx)

{

	return __raw_readl(cm_base + module + idx);

}



void cm_write_mod_reg(u32 val, s16 module, u16 idx)

void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)

{

	__raw_writel(val, cm_base + module + idx);

}



/* Read-modify-write a register in a CM module. Caller must lock */

u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)

u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)

{

	u32 v;



	v = cm_read_mod_reg(module, idx);

	v = omap2_cm_read_mod_reg(module, idx);

	v &= ~mask;

	v |= bits;

	cm_write_mod_reg(v, module, idx);

	omap2_cm_write_mod_reg(v, module, idx);



	return v;

}



u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)

u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)

{

	return cm_rmw_mod_reg_bits(bits, bits, module, idx);

	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);

}



u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)

u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)

{

	return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);

	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);

}



/**
@@ -90,7 +90,7 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) 
	else

		BUG();



	omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),

	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),

			  MAX_MODULE_READY_TIME, i);



	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -166,228 +166,238 @@ static struct omap3_cm_regs cm_context; 
void omap3_cm_save_context(void)

{

	cm_context.iva2_cm_clksel1 =

		cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);

	cm_context.iva2_cm_clksel2 =

		cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);

	cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);

	cm_context.sgx_cm_clksel =

		cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);

		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);

	cm_context.dss_cm_clksel =

		cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);

	cm_context.cam_cm_clksel =

		cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);

	cm_context.per_cm_clksel =

		cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);

	cm_context.emu_cm_clksel =

		cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);

		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);

	cm_context.emu_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.pll_cm_autoidle2 =

		cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);

		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);

	cm_context.pll_cm_clksel4 =

		cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);

		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);

	cm_context.pll_cm_clksel5 =

		cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);

		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);

	cm_context.pll_cm_clken2 =

		cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);

		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);

	cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);

	cm_context.iva2_cm_fclken =

		cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);

	cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,

						       OMAP3430_CM_CLKEN_PLL);

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);

	cm_context.iva2_cm_clken_pll =

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);

	cm_context.core_cm_fclken1 =

		cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);

		omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);

	cm_context.core_cm_fclken3 =

		cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);

		omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);

	cm_context.sgx_cm_fclken =

		cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);

	cm_context.wkup_cm_fclken =

		cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);

	cm_context.dss_cm_fclken =

		cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);

	cm_context.cam_cm_fclken =

		cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);

	cm_context.per_cm_fclken =

		cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);

	cm_context.usbhost_cm_fclken =

		cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);

		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);

	cm_context.core_cm_iclken1 =

		cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);

		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);

	cm_context.core_cm_iclken2 =

		cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);

		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);

	cm_context.core_cm_iclken3 =

		cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);

		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);

	cm_context.sgx_cm_iclken =

		cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);

	cm_context.wkup_cm_iclken =

		cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);

	cm_context.dss_cm_iclken =

		cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);

	cm_context.cam_cm_iclken =

		cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);

	cm_context.per_cm_iclken =

		cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);

	cm_context.usbhost_cm_iclken =

		cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);

		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);

	cm_context.iva2_cm_autoidle2 =

		cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);

	cm_context.mpu_cm_autoidle2 =

		cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);

		omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);

	cm_context.iva2_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.mpu_cm_clkstctrl =

		cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.core_cm_clkstctrl =

		cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.sgx_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.dss_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.cam_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.per_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.neon_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);

	cm_context.usbhost_cm_clkstctrl =

		cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);

		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,

				      OMAP2_CM_CLKSTCTRL);

	cm_context.core_cm_autoidle1 =

		cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);

		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);

	cm_context.core_cm_autoidle2 =

		cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);

		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);

	cm_context.core_cm_autoidle3 =

		cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);

		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);

	cm_context.wkup_cm_autoidle =

		cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);

		omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);

	cm_context.dss_cm_autoidle =

		cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);

	cm_context.cam_cm_autoidle =

		cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);

	cm_context.per_cm_autoidle =

		cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);

	cm_context.usbhost_cm_autoidle =

		cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);

		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);

	cm_context.sgx_cm_sleepdep =

		cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);

		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,

				      OMAP3430_CM_SLEEPDEP);

	cm_context.dss_cm_sleepdep =

		cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);

		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);

	cm_context.cam_cm_sleepdep =

		cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);

		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);

	cm_context.per_cm_sleepdep =

		cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);

		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);

	cm_context.usbhost_cm_sleepdep =

		cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);

		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,

				      OMAP3430_CM_SLEEPDEP);

	cm_context.cm_clkout_ctrl =

		cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET);

		omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,

				      OMAP3_CM_CLKOUT_CTRL_OFFSET);

}



void omap3_cm_restore_context(void)

{

	cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,

			       CM_CLKSEL1);

	cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,

			       CM_CLKSEL2);

	__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);

	cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,

	omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,

			       CM_CLKSEL);

	cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,

			       CM_CLKSEL);

	cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,

			       CM_CLKSEL);

	cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,

			       CM_CLKSEL);

	cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,

	omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,

			       CM_CLKSEL1);

	cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,

	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,

	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,

			       CM_AUTOIDLE2);

	cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,

	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,

			       OMAP3430ES2_CM_CLKSEL4);

	cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,

	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,

			       OMAP3430ES2_CM_CLKSEL5);

	cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,

	omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,

			       OMAP3430ES2_CM_CLKEN2);

	__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);

	cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,

			       CM_FCLKEN);

	cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,

			       OMAP3430_CM_CLKEN_PLL);

	cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);

	cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,

			       CM_FCLKEN1);

	omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,

			       OMAP3430ES2_CM_FCLKEN3);

	cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,

	omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,

			       CM_FCLKEN);

	cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);

	cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);

	omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,

			       CM_FCLKEN);

	cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,

			       CM_FCLKEN);

	cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,

			       CM_FCLKEN);

	cm_write_mod_reg(cm_context.usbhost_cm_fclken,

	omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,

			       OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);

	cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);

	cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);

	cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);

	cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,

			       CM_ICLKEN1);

	omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,

			       CM_ICLKEN2);

	omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,

			       CM_ICLKEN3);

	omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,

			       CM_ICLKEN);

	cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);

	cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);

	omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,

			       CM_ICLKEN);

	cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,

			       CM_ICLKEN);

	cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,

			       CM_ICLKEN);

	cm_write_mod_reg(cm_context.usbhost_cm_iclken,

	omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,

			       OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);

	cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,

			       CM_AUTOIDLE2);

	omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,

			       CM_AUTOIDLE2);

	cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);

	cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,

	omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,

	omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,

	omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,

	omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,

			       OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,

	omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,

			       OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);

	cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,

			       CM_AUTOIDLE1);

	cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,

			       CM_AUTOIDLE2);

	cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,

	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,

			       CM_AUTOIDLE3);

	cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,

			       CM_AUTOIDLE);

	omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,

			       CM_AUTOIDLE);

	cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,

			       CM_AUTOIDLE);

	cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,

			       CM_AUTOIDLE);

	cm_write_mod_reg(cm_context.usbhost_cm_autoidle,

	omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,

			       OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,

	omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,

			       OMAP3430_CM_SLEEPDEP);

	cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,

	omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,

			       OMAP3430_CM_SLEEPDEP);

	cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,

	omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,

			       OMAP3430_CM_SLEEPDEP);

	cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,

	omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,

			       OMAP3430_CM_SLEEPDEP);

	cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,

	omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,

			       OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);

	cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,

	omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,

			       OMAP3_CM_CLKOUT_CTRL_OFFSET);

}

#endif

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