ARM: at91: pm: revert do not disable/enable PLLA for ULP modes (c4cae59d) · Commits · 戴 / test

This reverts commit ("ARM: at91: pm: do not disable/enable PLLA for ULP modes"). This is because PLLA is the clock source for CPU, PLLA should be disabled/enabled in the final/first phase of suspend/resume so that the power consumption in suspend/resume to be minimal and suspend/resume time to be minimized. Signed-off-by:

Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by:

Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-3-git-send-email-claudiu.beznea@microchip.com

arch/arm/mach-at91/pm_suspend.S

+31 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,15 @@ tmp2 .req r5
		beq 1b
		.endm

		/*
		* Wait until PLLA has locked.
		*/
		.macro wait_pllalock
		1: ldr tmp1, [pmc, #AT91_PMC_SR]
		tst tmp1, #AT91_PMC_LOCKA
		beq 1b
		.endm

		/*
		* Put the processor to enter the idle state
		*/
		@@ -343,6 +352,14 @@ ENTRY(at91_ulp_mode)

		wait_mckrdy

		/* Save PLLA setting and disable it */
		ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
		str tmp1, .saved_pllar

		mov tmp1, #AT91_PMC_PLLCOUNT
		orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
		str tmp1, [pmc, #AT91_CKGR_PLLAR]

		ldr r0, .pm_mode
		cmp r0, #AT91_PM_ULP1
		beq ulp1_mode
		@@ -357,6 +374,18 @@ ulp1_mode:
		ulp_exit:
		ldr pmc, .pmc_base

		/* Restore PLLA setting */
		ldr tmp1, .saved_pllar
		str tmp1, [pmc, #AT91_CKGR_PLLAR]

		tst tmp1, #(AT91_PMC_MUL & 0xff0000)
		bne 3f
		tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
		beq 4f
		3:
		wait_pllalock
		4:

		/*
		* Restore master clock setting
		*/
		@@ -512,6 +541,8 @@ ENDPROC(at91_sramc_self_refresh)
		.word 0
		.saved_mckr:
		.word 0
		.saved_pllar:
		.word 0
		.saved_sam9_lpr:
		.word 0
		.saved_sam9_lpr1:

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