Commit c4c5ab30 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-fixes-for-linus' of... 

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (45 commits)
  x86, mce: fix error path in mce_create_device()
  x86: use zalloc_cpumask_var for mce_dev_initialized
  x86: fix duplicated sysfs attribute
  x86: de-assembler-ize asm/desc.h
  i386: fix/simplify espfix stack switching, move it into assembly
  i386: fix return to 16-bit stack from NMI handler
  x86, ioapic: Don't call disconnect_bsp_APIC if no APIC present
  x86: Remove duplicated #include's
  x86: msr.h linux/types.h is only required for __KERNEL__
  x86: nmi: Add Intel processor 0x6f4 to NMI perfctr1 workaround
  x86, mce: mce_intel.c needs <asm/apic.h>
  x86: apic/io_apic.c: dmar_msi_type should be static
  x86, io_apic.c: Work around compiler warning
  x86: mce: Don't touch THERMAL_APIC_VECTOR if no active APIC present
  x86: mce: Handle banks == 0 case in K7 quirk
  x86, boot: use .code16gcc instead of .code16
  x86: correct the conversion of EFI memory types
  x86: cap iomem_resource to addressable physical memory
  x86, mce: rename _64.c files which are no longer 64-bit-specific
  x86, mce: mce.h cleanup
  ...

Manually fix up trivial conflict in arch/x86/mm/fault.c
parents 7fd5b632 1d991001

arch/x86/boot/bioscall.S

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 * touching registers they shouldn't be.

 */



	.code16

	.code16gcc

	.text

	.globl	intcall

	.type	intcall, @function

arch/x86/include/asm/amd_iommu.h

+2 −0
Original line number Diff line number Diff line
@@ -29,9 +29,11 @@ extern void amd_iommu_detect(void); 
extern irqreturn_t amd_iommu_int_handler(int irq, void *data);

extern void amd_iommu_flush_all_domains(void);

extern void amd_iommu_flush_all_devices(void);

extern void amd_iommu_shutdown(void);

#else

static inline int amd_iommu_init(void) { return -ENODEV; }

static inline void amd_iommu_detect(void) { }

static inline void amd_iommu_shutdown(void) { }

#endif



#endif /* _ASM_X86_AMD_IOMMU_H */

arch/x86/include/asm/atomic_32.h

+1 −2
Original line number Diff line number Diff line
@@ -257,7 +257,7 @@ typedef struct { 


/**

 * atomic64_read - read atomic64 variable

 * @v: pointer of type atomic64_t

 * @ptr: pointer of type atomic64_t

 *

 * Atomically reads the value of @v.

 * Doesn't imply a read memory barrier.
@@ -294,7 +294,6 @@ atomic64_cmpxchg(atomic64_t *ptr, unsigned long long old_val, 
 * atomic64_xchg - xchg atomic64 variable

 * @ptr:      pointer to type atomic64_t

 * @new_val:  value to assign

 * @old_val:  old value that was there

 *

 * Atomically xchgs the value of @ptr to @new_val and returns

 * the old value.

arch/x86/include/asm/desc.h

+0 −26
Original line number Diff line number Diff line 
#ifndef _ASM_X86_DESC_H

#define _ASM_X86_DESC_H



#ifndef __ASSEMBLY__

#include <asm/desc_defs.h>

#include <asm/ldt.h>

#include <asm/mmu.h>
@@ -380,29 +379,4 @@ static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist) 
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);

}



#else

/*

 * GET_DESC_BASE reads the descriptor base of the specified segment.

 *

 * Args:

 *    idx - descriptor index

 *    gdt - GDT pointer

 *    base - 32bit register to which the base will be written

 *    lo_w - lo word of the "base" register

 *    lo_b - lo byte of the "base" register

 *    hi_b - hi byte of the low word of the "base" register

 *

 * Example:

 *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)

 *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.

 */

#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \

	movb idx * 8 + 4(gdt), lo_b;			\

	movb idx * 8 + 7(gdt), hi_b;			\

	shll $16, base;					\

	movw idx * 8 + 2(gdt), lo_w;





#endif /* __ASSEMBLY__ */



#endif /* _ASM_X86_DESC_H */

arch/x86/include/asm/mce.h

+51 −12
Original line number Diff line number Diff line
@@ -102,15 +102,39 @@ struct mce_log { 


#ifdef __KERNEL__



#include <linux/percpu.h>

#include <linux/init.h>

#include <asm/atomic.h>



extern int mce_disabled;

extern int mce_p5_enabled;



#include <asm/atomic.h>

#include <linux/percpu.h>

#ifdef CONFIG_X86_MCE

void mcheck_init(struct cpuinfo_x86 *c);

#else

static inline void mcheck_init(struct cpuinfo_x86 *c) {}

#endif



#ifdef CONFIG_X86_OLD_MCE

extern int nr_mce_banks;

void amd_mcheck_init(struct cpuinfo_x86 *c);

void intel_p4_mcheck_init(struct cpuinfo_x86 *c);

void intel_p6_mcheck_init(struct cpuinfo_x86 *c);

#endif



#ifdef CONFIG_X86_ANCIENT_MCE

void intel_p5_mcheck_init(struct cpuinfo_x86 *c);

void winchip_mcheck_init(struct cpuinfo_x86 *c);

static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }

#else

static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}

static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}

static inline void enable_p5_mce(void) {}

#endif



void mce_setup(struct mce *m);

void mce_log(struct mce *m);

DECLARE_PER_CPU(struct sys_device, mce_dev);

extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);



/*

 * To support more than 128 would need to escape the predefined
@@ -145,12 +169,8 @@ int mce_available(struct cpuinfo_x86 *c); 
DECLARE_PER_CPU(unsigned, mce_exception_count);

DECLARE_PER_CPU(unsigned, mce_poll_count);



void mce_log_therm_throt_event(__u64 status);



extern atomic_t mce_entry;



void do_machine_check(struct pt_regs *, long);



typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);

DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
@@ -167,13 +187,32 @@ void mce_notify_process(void); 
DECLARE_PER_CPU(struct mce, injectm);

extern struct file_operations mce_chrdev_ops;



#ifdef CONFIG_X86_MCE

void mcheck_init(struct cpuinfo_x86 *c);

#else

#define mcheck_init(c) do { } while (0)

#endif

/*

 * Exception handler

 */



/* Call the installed machine check handler for this CPU setup. */

extern void (*machine_check_vector)(struct pt_regs *, long error_code);

void do_machine_check(struct pt_regs *, long);



/*

 * Threshold handler

 */



extern void (*mce_threshold_vector)(void);

extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);



/*

 * Thermal handler

 */



void intel_init_thermal(struct cpuinfo_x86 *c);



#ifdef CONFIG_X86_NEW_MCE

void mce_log_therm_throt_event(__u64 status);

#else

static inline void mce_log_therm_throt_event(__u64 status) {}

#endif



#endif /* __KERNEL__ */

#endif /* _ASM_X86_MCE_H */

CRA Git | Maintained and supported by SUSTech CRA and CCSE