EDAC, amd64: Add Hygon Dhyana support (c4a3e946) · Commits · 戴 / test

drivers/edac/amd64_edac.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)

		scrubval = scrubrates[i].scrubval;

		if (pvt->fam == 0x17) {
		if (pvt->fam == 0x17 \|\| pvt->fam == 0x18) {
		__f17h_set_scrubval(pvt, scrubval);
		} else if (pvt->fam == 0x15 && pvt->model == 0x60) {
		f15h_select_dct(pvt, 0);
		@@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
		break;

		case 0x17:
		case 0x18:
		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
		if (scrubval & BIT(0)) {
		amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
		@@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt)
		goto ddr3;

		case 0x17:
		case 0x18:
		if ((pvt->umc[0].dimm_cfg \| pvt->umc[1].dimm_cfg) & BIT(5))
		pvt->dram_type = MEM_LRDDR4;
		else if ((pvt->umc[0].dimm_cfg \| pvt->umc[1].dimm_cfg) & BIT(4))
		@@ -3202,8 +3204,13 @@ static struct amd64_family_type per_family_init(struct amd64_pvt pvt)
		pvt->ops = &family_types[F17_M10H_CPUS].ops;
		break;
		}
		/* fall through */
		case 0x18:
		fam_type = &family_types[F17_CPUS];
		pvt->ops = &family_types[F17_CPUS].ops;

		if (pvt->fam == 0x18)
		family_types[F17_CPUS].ctl_name = "F18h";
		break;

		default:
		@@ -3442,6 +3449,7 @@ static const struct x86_cpu_id amd64_cpuids[] = {
		{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
		{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
		{ X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
		{ X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
		{ }
		};
		MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);

drivers/edac/mce_amd.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -1059,7 +1059,8 @@ static int __init mce_amd_init(void)
		{
		struct cpuinfo_x86 *c = &boot_cpu_data;

		if (c->x86_vendor != X86_VENDOR_AMD)
		if (c->x86_vendor != X86_VENDOR_AMD &&
		c->x86_vendor != X86_VENDOR_HYGON)
		return -ENODEV;

		fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
		@@ -1113,6 +1114,7 @@ static int __init mce_amd_init(void)
		break;

		case 0x17:
		case 0x18:
		xec_mask = 0x3f;
		if (!boot_cpu_has(X86_FEATURE_SMCA)) {
		printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");

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