Commit c49f60df authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Andrzej Hajda
Browse files

drm/bridge: tc358767: Introduce tc_set_syspllparam() 



Move common code converting clock rate to an appropriate constant and
configuring SYS_PLLPARAM register into a separate routine and convert
the rest of the code to use it. No functional change intended.

Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619052716.16831-11-andrew.smirnov@gmail.com
parent 12dfe7c4

drivers/gpu/drm/bridge/tc358767.c

+16 −30
Original line number Diff line number Diff line
@@ -556,35 +556,40 @@ static int tc_stream_clock_calc(struct tc_data *tc) 
	return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);

}



static int tc_aux_link_setup(struct tc_data *tc)

static int tc_set_syspllparam(struct tc_data *tc)

{

	unsigned long rate;

	u32 dp0_auxcfg1;

	u32 value;

	int ret;

	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;



	rate = clk_get_rate(tc->refclk);

	switch (rate) {

	case 38400000:

		value = REF_FREQ_38M4;

		pllparam |= REF_FREQ_38M4;

		break;

	case 26000000:

		value = REF_FREQ_26M;

		pllparam |= REF_FREQ_26M;

		break;

	case 19200000:

		value = REF_FREQ_19M2;

		pllparam |= REF_FREQ_19M2;

		break;

	case 13000000:

		value = REF_FREQ_13M;

		pllparam |= REF_FREQ_13M;

		break;

	default:

		dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);

		return -EINVAL;

	}



	return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);

}



static int tc_aux_link_setup(struct tc_data *tc)

{

	int ret;

	u32 dp0_auxcfg1;



	/* Setup DP-PHY / PLL */

	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);

	ret = tc_set_syspllparam(tc);

	if (ret)

		goto err;
@@ -843,7 +848,6 @@ static int tc_main_link_enable(struct tc_data *tc) 
{

	struct drm_dp_aux *aux = &tc->aux;

	struct device *dev = tc->dev;

	unsigned int rate;

	u32 dp_phy_ctrl;

	u32 value;

	int ret;
@@ -871,25 +875,7 @@ static int tc_main_link_enable(struct tc_data *tc) 
	if (ret)

		return ret;



	rate = clk_get_rate(tc->refclk);

	switch (rate) {

	case 38400000:

		value = REF_FREQ_38M4;

		break;

	case 26000000:

		value = REF_FREQ_26M;

		break;

	case 19200000:

		value = REF_FREQ_19M2;

		break;

	case 13000000:

		value = REF_FREQ_13M;

		break;

	default:

		return -EINVAL;

	}

	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);

	ret = tc_set_syspllparam(tc);

	if (ret)

		return ret;

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