Commit c463b8cb authored by Myron Stowe's avatar Myron Stowe Committed by Bjorn Helgaas
Browse files

PCI: add pci_pcie_cap2() check for PCIe feature capabilities >= v2 



This patch resolves potential issues when accessing PCI Express
Capability structures.  The makeup of the capability varies
substantially between v1 and v2:

    Version 1 of the PCI Express Capability (defined by PCI Express
    1.0 and 1.1 base) neither requires the endpoint to implement the
    entire PCIe capability structure nor specifies default values of
    registers that are not implemented by the device.

    Version 2 of the PCI Express Capability (defined by PCIe 1.1
    Capability Structure Expansion ECN, PCIe 2.0, 2.1, and 3.0) added
    additional registers to the structure and requires all registers
    to be either implemented or hardwired to 0.

Due to the differences in the capability structures, code dealing with
capability features must be careful not to access the additional
registers introduced with v2 unless the device is specifically known to
be a v2 capable device.  Otherwise, attempts to access non-existant
registers will occur.  This is a subtle issue that is hard to track down
when it occurs (and it has - see commit 864d296c).

To try and help mitigate such occurrences, this patch introduces
pci_pcie_cap2() which is similar to pci_pcie_cap() but also checks
that the PCIe capability version is >= 2.  pci_pcie_cap2() should be
used for qualifying PCIe capability features introduced after v1.

Suggested by Don Dutile.

Acked-by: default avatarDonald Dutile <ddutile@redhat.com>
Signed-off-by: default avatarMyron Stowe <myron.stowe@redhat.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent cb97ae34

drivers/pci/pci.c

+50 −15
Original line number Diff line number Diff line
@@ -277,6 +277,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 
	return pos;

}



/**

 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure

 * @dev: PCI device to check

 *

 * Like pci_pcie_cap() but also checks that the PCIe capability version is

 * >= 2.  Note that v1 capability structures could be sparse in that not

 * all register fields were required.  v2 requires the entire structure to

 * be present size wise, while still allowing for non-implemented registers

 * to exist but they must be hardwired to 0.

 *

 * Due to the differences in the versions of capability structures, one

 * must be careful not to try and access non-existant registers that may

 * exist in early versions - v1 - of Express devices.

 *

 * Returns the offset of the PCIe capability structure as long as the

 * capability version is >= 2; otherwise 0 is returned.

 */

static int pci_pcie_cap2(struct pci_dev *dev)

{

	u16 flags;

	int pos;



	pos = pci_pcie_cap(dev);

	if (pos) {

		pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);

		if ((flags & PCI_EXP_FLAGS_VERS) < 2)

			pos = 0;

	}



	return pos;

}



/**

 * pci_find_ext_capability - Find an extended capability

 * @dev: PCI device to query
@@ -1983,7 +2015,7 @@ void pci_enable_ari(struct pci_dev *dev) 
{

	int pos;

	u32 cap;

	u16 flags, ctrl;

	u16 ctrl;

	struct pci_dev *bridge;



	if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
@@ -1997,15 +2029,11 @@ void pci_enable_ari(struct pci_dev *dev) 
	if (!bridge)

		return;



	pos = pci_pcie_cap(bridge);

	/* ARI is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(bridge);

	if (!pos)

		return;



	/* ARI is a PCIe v2 feature */

	pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);

	if ((flags & PCI_EXP_FLAGS_VERS) < 2)

		return;



	pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);

	if (!(cap & PCI_EXP_DEVCAP2_ARI))

		return;
@@ -2018,7 +2046,7 @@ void pci_enable_ari(struct pci_dev *dev) 
}



/**

 * pci_enable_ido - enable ID-based ordering on a device

 * pci_enable_ido - enable ID-based Ordering on a device

 * @dev: the PCI device

 * @type: which types of IDO to enable

 *
@@ -2031,7 +2059,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type) 
	int pos;

	u16 ctrl;



	pos = pci_pcie_cap(dev);

	/* ID-based Ordering is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return;
@@ -2054,7 +2083,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type) 
	int pos;

	u16 ctrl;



	pos = pci_pcie_cap(dev);

	/* ID-based Ordering is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return;
@@ -2093,7 +2123,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 
	u16 ctrl;

	int ret;



	pos = pci_pcie_cap(dev);

	/* OBFF is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return -ENOTSUPP;
@@ -2143,7 +2174,8 @@ void pci_disable_obff(struct pci_dev *dev) 
	int pos;

	u16 ctrl;



	pos = pci_pcie_cap(dev);

	/* OBFF is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return;
@@ -2165,7 +2197,8 @@ static bool pci_ltr_supported(struct pci_dev *dev) 
	int pos;

	u32 cap;



	pos = pci_pcie_cap(dev);

	/* LTR is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return false;
@@ -2193,7 +2226,8 @@ int pci_enable_ltr(struct pci_dev *dev) 
	if (!pci_ltr_supported(dev))

		return -ENOTSUPP;



	pos = pci_pcie_cap(dev);

	/* LTR is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return -ENOTSUPP;
@@ -2228,7 +2262,8 @@ void pci_disable_ltr(struct pci_dev *dev) 
	if (!pci_ltr_supported(dev))

		return;



	pos = pci_pcie_cap(dev);

	/* LTR is a PCIe cap v2 feature */

	pos = pci_pcie_cap2(dev);

	if (!pos)

		return;

include/linux/pci_regs.h

+6 −0
Original line number Diff line number Diff line
@@ -507,6 +507,12 @@ 
#define PCI_EXP_RTSTA		32	/* Root Status */

#define PCI_EXP_RTSTA_PME	0x10000 /* PME status */

#define PCI_EXP_RTSTA_PENDING	0x20000 /* PME pending */

/*

 * Note that the following PCI Express 'Capability Structure' registers

 * were introduced with 'Capability Version' 0x2 (v2).  These registers

 * do not exist on devices with Capability Version 1.  Use pci_pcie_cap2()

 * to use these fields safely.

 */

#define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */

#define  PCI_EXP_DEVCAP2_ARI	0x20	/* Alternative Routing-ID */

#define  PCI_EXP_DEVCAP2_LTR	0x800	/* Latency tolerance reporting */

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