Commit c4621988 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: Add dprefclk value to dce_dccg



This allows us to avoid any vbios bugs when initializing clocks

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 94a4ffd1
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+3 −1
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ static int dce12_get_dp_ref_freq_khz(struct dccg *clk)
{
	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);
	return dccg_adjust_dp_ref_freq_for_ss(clk_dce, clk_dce->dprefclk_khz);
}

static enum dm_pp_clocks_state dce_get_required_clocks_state(
@@ -882,6 +882,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
	dce_dccg_construct(
		clk_dce, ctx, NULL, NULL, NULL);

	clk_dce->dprefclk_khz = 600000;
	clk_dce->base.funcs = &dce120_funcs;

	return &clk_dce->base;
@@ -909,6 +910,7 @@ struct dccg *dcn1_dccg_create(struct dc_context *ctx)
	clk_dce->dprefclk_ss_divider = 1000;
	clk_dce->ss_on_dprefclk = false;

	clk_dce->dprefclk_khz = 600000;
	if (bp->integrated_info)
		clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
	if (clk_dce->dentist_vco_freq_khz == 0) {
+1 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ struct dce_dccg {
	int dprefclk_ss_percentage;
	/* DPREFCLK SS percentage Divider (100 or 1000) */
	int dprefclk_ss_divider;
	int dprefclk_khz;
};