Commit c45ae598 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Stephen Boyd
Browse files

clk: qcom: support for alpha mode configuration 



The current configuration does not fully configure PLL alpha mode
and values so this patch

1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha.
2. Adds alpha enable and alpha mode configuration support.

Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 26945e0a

drivers/clk/qcom/clk-alpha-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -143,6 +143,9 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

			     config->config_ctl_hi_val);



	if (pll_alpha_width(pll) > 32)

		regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);



	val = config->main_output_mask;

	val |= config->aux_output_mask;

	val |= config->aux2_output_mask;
@@ -150,6 +153,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
	val |= config->pre_div_val;

	val |= config->post_div_val;

	val |= config->vco_val;

	val |= config->alpha_en_mask;

	val |= config->alpha_mode_mask;



	mask = config->main_output_mask;

	mask |= config->aux_output_mask;

drivers/clk/qcom/clk-alpha-pll.h

+3 −0
Original line number Diff line number Diff line
@@ -83,12 +83,15 @@ struct clk_alpha_pll_postdiv { 
struct alpha_pll_config {

	u32 l;

	u32 alpha;

	u32 alpha_hi;

	u32 config_ctl_val;

	u32 config_ctl_hi_val;

	u32 main_output_mask;

	u32 aux_output_mask;

	u32 aux2_output_mask;

	u32 early_output_mask;

	u32 alpha_en_mask;

	u32 alpha_mode_mask;

	u32 pre_div_val;

	u32 pre_div_mask;

	u32 post_div_val;

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