Commit c4541946 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'zynq-cleanup-for-3.12' of git://git.xilinx.com/linux-xlnx into next/cleanup 

From: Michal Simek:
arm: Xilinx Zynq cleanup patches for v3.12

This branch contains these fixes:
- SLCR cleanup
- Hotplug cleanup

* tag 'zynq-cleanup-for-3.12' of git://git.xilinx.com/linux-xlnx

:
  arm: zynq: hotplug: Remove unreachable code
  arm: zynq: slcr: Use read-modify-write for register writes
  arm: zynq: slcr: Clean up #defines
  arm: zynq: slcr: Remove redundant header #includes

Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parents 47aad66c b522877b

arch/arm/mach-zynq/hotplug.c

+5 −50
Original line number Diff line number Diff line
@@ -40,44 +40,6 @@ static inline void zynq_cpu_enter_lowpower(void) 
	  : "cc");

}



static inline void zynq_cpu_leave_lowpower(void)

{

	unsigned int v;



	asm volatile(

	"	mrc	p15, 0, %0, c1, c0, 0\n"

	"	orr	%0, %0, %1\n"

	"	mcr	p15, 0, %0, c1, c0, 0\n"

	"	mrc	p15, 0, %0, c1, c0, 1\n"

	"	orr	%0, %0, #0x40\n"

	"	mcr	p15, 0, %0, c1, c0, 1\n"

	  : "=&r" (v)

	  : "Ir" (CR_C)

	  : "cc");

}



static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)

{

	/*

	 * there is no power-control hardware on this platform, so all

	 * we can do is put the core into WFI; this is safe as the calling

	 * code will have already disabled interrupts

	 */

	for (;;) {

		dsb();

		wfi();



		/*

		 * Getting here, means that we have come out of WFI without

		 * having been woken up - this shouldn't happen

		 *

		 * Just note it happening - when we're woken, we can report

		 * its occurrence.

		 */

		(*spurious)++;

	}

}



/*

 * platform-specific code to shutdown a CPU

 *
@@ -85,20 +47,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious) 
 */

void zynq_platform_cpu_die(unsigned int cpu)

{

	int spurious = 0;



	/*

	 * we're ready for shutdown now, so do it

	 */

	zynq_cpu_enter_lowpower();

	zynq_platform_do_lowpower(cpu, &spurious);



	/*

	 * bring this CPU back into the world of cache

	 * coherency, and then restore interrupts

	 * there is no power-control hardware on this platform, so all

	 * we can do is put the core into WFI; this is safe as the calling

	 * code will have already disabled interrupts

	 */

	zynq_cpu_leave_lowpower();



	if (spurious)

		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);

	for (;;)

		cpu_do_idle();

}

arch/arm/mach-zynq/slcr.c

+17 −28
Original line number Diff line number Diff line
@@ -14,32 +14,21 @@ 
 * 02139, USA.

 */



#include <linux/export.h>

#include <linux/io.h>

#include <linux/fs.h>

#include <linux/interrupt.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/uaccess.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/string.h>

#include <linux/clk/zynq.h>

#include "common.h"



#define SLCR_UNLOCK_MAGIC		0xDF0D

#define SLCR_UNLOCK			0x8   /* SCLR unlock register */



/* register offsets */

#define SLCR_UNLOCK_OFFSET		0x8   /* SCLR unlock register */

#define SLCR_PS_RST_CTRL_OFFSET		0x200 /* PS Software Reset Control */

#define SLCR_A9_CPU_RST_CTRL_OFFSET	0x244 /* CPU Software Reset Control */

#define SLCR_REBOOT_STATUS_OFFSET	0x258 /* PS Reboot Status */



#define SLCR_UNLOCK_MAGIC		0xDF0D

#define SLCR_A9_CPU_CLKSTOP		0x10

#define SLCR_A9_CPU_RST			0x1



#define SLCR_A9_CPU_RST_CTRL		0x244 /* CPU Software Reset Control */

#define SLCR_REBOOT_STATUS		0x258 /* PS Reboot Status */



void __iomem *zynq_slcr_base;



/**
@@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void) 
	 * Note that this seems to require raw i/o

	 * functions or there's a lockup?

	 */

	writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);

	writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);



	/*

	 * Clear 0x0F000000 bits of reboot status register to workaround

	 * the FSBL not loading the bitstream after soft-reboot

	 * This is a temporary solution until we know more.

	 */

	reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);

	writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);

	reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);

	writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);

	writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);

}
@@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void) 
 */

void zynq_slcr_cpu_start(int cpu)

{

	/* enable CPUn */

	writel(SLCR_A9_CPU_CLKSTOP << cpu,

	       zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);

	/* enable CLK for CPUn */

	writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);

	u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg &= ~(SLCR_A9_CPU_RST << cpu);

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

}



/**
@@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) 
 */

void zynq_slcr_cpu_stop(int cpu)

{

	/* stop CLK and reset CPUn */

	writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,

	       zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);

	u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

}



/**
@@ -113,7 +102,7 @@ int __init zynq_slcr_init(void) 
	}



	/* unlock the SLCR so that registers can be changed */

	writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);

	writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);



	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);

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