Commit c43ff6a8 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.7-cpuidle' of... 

Merge tag 'tegra-for-5.7-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

cpuidle: tegra: Changes for v5.7-rc1

These changes unify CPU idle support for Tegra20, Tegra30 and Tegra114.

* tag 'tegra-for-5.7-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  cpuidle: tegra: Disable CC6 state if LP2 unavailable
  cpuidle: tegra: Squash Tegra114 driver into the common driver
  cpuidle: tegra: Squash Tegra30 driver into the common driver
  cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle

Link: https://lore.kernel.org/r/20200313165848.2915133-9-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 880e1929 382ac8e2

arch/arm/mach-tegra/Makefile

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Original line number Diff line number Diff line
@@ -10,25 +10,12 @@ obj-y += sleep.o 
obj-y					+= tegra.o

obj-y					+= sleep-tegra20.o

obj-y					+= sleep-tegra30.o

obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pm-tegra20.o

ifeq ($(CONFIG_CPU_IDLE),y)

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= cpuidle-tegra20.o

endif

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pm-tegra30.o

ifeq ($(CONFIG_CPU_IDLE),y)

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= cpuidle-tegra30.o

endif

obj-$(CONFIG_SMP)			+= platsmp.o

obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o



obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= pm-tegra30.o

ifeq ($(CONFIG_CPU_IDLE),y)

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o

endif

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= pm-tegra30.o

ifeq ($(CONFIG_CPU_IDLE),y)

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= cpuidle-tegra114.o

endif



obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o

arch/arm/mach-tegra/cpuidle-tegra114.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.

 */



#include <asm/firmware.h>

#include <linux/tick.h>

#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/kernel.h>

#include <linux/module.h>



#include <linux/firmware/trusted_foundations.h>



#include <soc/tegra/pm.h>



#include <asm/cpuidle.h>

#include <asm/smp_plat.h>

#include <asm/suspend.h>

#include <asm/psci.h>



#include "cpuidle.h"

#include "sleep.h"



#ifdef CONFIG_PM_SLEEP

#define TEGRA114_MAX_STATES 2

#else

#define TEGRA114_MAX_STATES 1

#endif



#ifdef CONFIG_PM_SLEEP

static int tegra114_idle_power_down(struct cpuidle_device *dev,

				    struct cpuidle_driver *drv,

				    int index)

{

	local_fiq_disable();



	tegra_pm_set_cpu_in_lp2();

	cpu_pm_enter();



	call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);



	/* Do suspend by ourselves if the firmware does not implement it */

	if (call_firmware_op(do_idle, 0) == -ENOSYS)

		cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);



	cpu_pm_exit();

	tegra_pm_clear_cpu_in_lp2();



	local_fiq_enable();



	return index;

}



static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev,

				       struct cpuidle_driver *drv,

				       int index)

{

       tegra114_idle_power_down(dev, drv, index);

}

#endif



static struct cpuidle_driver tegra_idle_driver = {

	.name = "tegra_idle",

	.owner = THIS_MODULE,

	.state_count = TEGRA114_MAX_STATES,

	.states = {

		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

#ifdef CONFIG_PM_SLEEP

		[1] = {

			.enter			= tegra114_idle_power_down,

			.enter_s2idle		= tegra114_idle_enter_s2idle,

			.exit_latency		= 500,

			.target_residency	= 1000,

			.flags			= CPUIDLE_FLAG_TIMER_STOP,

			.power_usage		= 0,

			.name			= "powered-down",

			.desc			= "CPU power gated",

		},

#endif

	},

};



int __init tegra114_cpuidle_init(void)

{

	if (!psci_smp_available())

		return cpuidle_register(&tegra_idle_driver, NULL);



	return 0;

}

arch/arm/mach-tegra/cpuidle-tegra20.c

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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * CPU idle driver for Tegra CPUs

 *

 * Copyright (c) 2010-2012, NVIDIA Corporation.

 * Copyright (c) 2011 Google, Inc.

 * Author: Colin Cross <ccross@android.com>

 *         Gary King <gking@nvidia.com>

 *

 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>

 */



#include <linux/clk/tegra.h>

#include <linux/tick.h>

#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/module.h>



#include <soc/tegra/flowctrl.h>

#include <soc/tegra/irq.h>

#include <soc/tegra/pm.h>



#include <asm/cpuidle.h>

#include <asm/smp_plat.h>

#include <asm/suspend.h>



#include "cpuidle.h"

#include "iomap.h"

#include "reset.h"

#include "sleep.h"



#ifdef CONFIG_PM_SLEEP

static atomic_t abort_flag;

static atomic_t abort_barrier;

static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,

				    struct cpuidle_driver *drv,

				    int index);

#define TEGRA20_MAX_STATES 2

#else

#define TEGRA20_MAX_STATES 1

#endif



static struct cpuidle_driver tegra_idle_driver = {

	.name = "tegra_idle",

	.owner = THIS_MODULE,

	.states = {

		ARM_CPUIDLE_WFI_STATE_PWR(600),

#ifdef CONFIG_PM_SLEEP

		{

			.enter            = tegra20_idle_lp2_coupled,

			.exit_latency     = 5000,

			.target_residency = 10000,

			.power_usage      = 0,

			.flags            = CPUIDLE_FLAG_COUPLED |

			                    CPUIDLE_FLAG_TIMER_STOP,

			.name             = "powered-down",

			.desc             = "CPU power gated",

		},

#endif

	},

	.state_count = TEGRA20_MAX_STATES,

	.safe_state_index = 0,

};



#ifdef CONFIG_PM_SLEEP

#ifdef CONFIG_SMP

static void tegra20_wake_cpu1_from_reset(void)

{

	/* enable cpu clock on cpu */

	tegra_enable_cpu_clock(1);



	/* take the CPU out of reset */

	tegra_cpu_out_of_reset(1);



	/* unhalt the cpu */

	flowctrl_write_cpu_halt(1, 0);

}

#else

static inline void tegra20_wake_cpu1_from_reset(void)

{

}

#endif



static void tegra20_report_cpus_state(void)

{

	unsigned long cpu, lcpu, csr;



	for_each_cpu(lcpu, cpu_possible_mask) {

		cpu = cpu_logical_map(lcpu);

		csr = flowctrl_read_cpu_csr(cpu);



		pr_err("cpu%lu: online=%d flowctrl_csr=0x%08lx\n",

		       cpu, cpu_online(lcpu), csr);

	}

}



static int tegra20_wait_for_secondary_cpu_parking(void)

{

	unsigned int retries = 3;



	while (retries--) {

		unsigned int delay_us = 10;

		unsigned int timeout_us = 500 * 1000 / delay_us;



		/*

		 * The primary CPU0 core shall wait for the secondaries

		 * shutdown in order to power-off CPU's cluster safely.

		 * The timeout value depends on the current CPU frequency,

		 * it takes about 40-150us  in average and over 1000us in

		 * a worst case scenario.

		 */

		do {

			if (tegra_cpu_rail_off_ready())

				return 0;



			udelay(delay_us);



		} while (timeout_us--);



		pr_err("secondary CPU taking too long to park\n");



		tegra20_report_cpus_state();

	}



	pr_err("timed out waiting secondaries to park\n");



	return -ETIMEDOUT;

}



static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,

					   struct cpuidle_driver *drv,

					   int index)

{

	bool ret;



	if (tegra20_wait_for_secondary_cpu_parking())

		return false;



	ret = !tegra_pm_enter_lp2();



	if (cpu_online(1))

		tegra20_wake_cpu1_from_reset();



	return ret;

}



#ifdef CONFIG_SMP

static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,

					 struct cpuidle_driver *drv,

					 int index)

{

	cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu);



	return true;

}

#else

static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,

						struct cpuidle_driver *drv,

						int index)

{

	return true;

}

#endif



static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,

				    struct cpuidle_driver *drv,

				    int index)

{

	bool entered_lp2 = false;



	if (tegra_pending_sgi())

		atomic_set(&abort_flag, 1);



	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);



	if (atomic_read(&abort_flag)) {

		cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

		/* clean flag for next coming */

		atomic_set(&abort_flag, 0);

		return -EINTR;

	}



	local_fiq_disable();



	tegra_pm_set_cpu_in_lp2();

	cpu_pm_enter();



	if (dev->cpu == 0)

		entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);

	else

		entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);



	cpu_pm_exit();

	tegra_pm_clear_cpu_in_lp2();



	local_fiq_enable();



	return entered_lp2 ? index : 0;

}

#endif



/*

 * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether

 * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around

 * this, simply disable LP2 if the PCI driver and DT node are both enabled.

 */

void tegra20_cpuidle_pcie_irqs_in_use(void)

{

	pr_info_once(

		"Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");

	cpuidle_driver_state_disabled(&tegra_idle_driver, 1, true);

}



int __init tegra20_cpuidle_init(void)

{

	return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);

}

arch/arm/mach-tegra/cpuidle-tegra30.c

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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * CPU idle driver for Tegra CPUs

 *

 * Copyright (c) 2010-2012, NVIDIA Corporation.

 * Copyright (c) 2011 Google, Inc.

 * Author: Colin Cross <ccross@android.com>

 *         Gary King <gking@nvidia.com>

 *

 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>

 */



#include <linux/clk/tegra.h>

#include <linux/tick.h>

#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/kernel.h>

#include <linux/module.h>



#include <soc/tegra/pm.h>



#include <asm/cpuidle.h>

#include <asm/smp_plat.h>

#include <asm/suspend.h>



#include "cpuidle.h"

#include "sleep.h"



#ifdef CONFIG_PM_SLEEP

static int tegra30_idle_lp2(struct cpuidle_device *dev,

			    struct cpuidle_driver *drv,

			    int index);

#endif



static struct cpuidle_driver tegra_idle_driver = {

	.name = "tegra_idle",

	.owner = THIS_MODULE,

#ifdef CONFIG_PM_SLEEP

	.state_count = 2,

#else

	.state_count = 1,

#endif

	.states = {

		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

#ifdef CONFIG_PM_SLEEP

		[1] = {

			.enter			= tegra30_idle_lp2,

			.exit_latency		= 2000,

			.target_residency	= 2200,

			.power_usage		= 0,

			.flags			= CPUIDLE_FLAG_TIMER_STOP,

			.name			= "powered-down",

			.desc			= "CPU power gated",

		},

#endif

	},

};



#ifdef CONFIG_PM_SLEEP

static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,

					   struct cpuidle_driver *drv,

					   int index)

{

	/* All CPUs entering LP2 is not working.

	 * Don't let CPU0 enter LP2 when any secondary CPU is online.

	 */

	if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {

		cpu_do_idle();

		return false;

	}



	return !tegra_pm_enter_lp2();

}



#ifdef CONFIG_SMP

static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,

					struct cpuidle_driver *drv,

					int index)

{

	smp_wmb();



	cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);



	return true;

}

#else

static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,

					       struct cpuidle_driver *drv,

					       int index)

{

	return true;

}

#endif



static int tegra30_idle_lp2(struct cpuidle_device *dev,

			    struct cpuidle_driver *drv,

			    int index)

{

	bool entered_lp2 = false;



	local_fiq_disable();



	tegra_pm_set_cpu_in_lp2();

	cpu_pm_enter();



	if (dev->cpu == 0)

		entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);

	else

		entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);



	cpu_pm_exit();

	tegra_pm_clear_cpu_in_lp2();



	local_fiq_enable();



	return (entered_lp2) ? index : 0;

}

#endif



int __init tegra30_cpuidle_init(void)

{

	return cpuidle_register(&tegra_idle_driver, NULL);

}

arch/arm/mach-tegra/cpuidle.c

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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * arch/arm/mach-tegra/cpuidle.c

 *

 * CPU idle driver for Tegra CPUs

 *

 * Copyright (c) 2010-2012, NVIDIA Corporation.

 * Copyright (c) 2011 Google, Inc.

 * Author: Colin Cross <ccross@android.com>

 *         Gary King <gking@nvidia.com>

 *

 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>

 */



#include <linux/kernel.h>

#include <linux/module.h>



#include <soc/tegra/fuse.h>



#include "cpuidle.h"



void __init tegra_cpuidle_init(void)

{

	switch (tegra_get_chip_id()) {

	case TEGRA20:

		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))

			tegra20_cpuidle_init();

		break;

	case TEGRA30:

		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))

			tegra30_cpuidle_init();

		break;

	case TEGRA114:

	case TEGRA124:

		if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||

		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))

			tegra114_cpuidle_init();

		break;

	}

}



void tegra_cpuidle_pcie_irqs_in_use(void)

{

	switch (tegra_get_chip_id()) {

	case TEGRA20:

		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))

			tegra20_cpuidle_pcie_irqs_in_use();

		break;

	}

}

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