Commit c40d1cce authored Oct 18, 2019 by Nava kishore Manne Committed by Michal Simek Oct 23, 2019

arm64: zynqmp: Label whole PL part as fpga_full region



This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>

parent 9c363392

arch/arm64/boot/dts/xilinx/zynqmp.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -135,6 +135,14 @@
		<1 10 0xf08>;
		};

		fpga_full: fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <&zynqmp_pcap>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		};

		amba_apu: amba-apu@0 {
		compatible = "simple-bus";
		#address-cells = <2>;

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