Commit c3e757a7 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: [tlb-miss] Extraneous PTE bit testing/setting 



* No need to check for READ access in I-TLB Miss handler

* Redundant PAGE_PRESENT update in PTE

Post TLB entry installation, in updating PTE for software accessed/dity
bits, no need to update PAGE_PRESENT since it will already be set.
Infact the entry won't have installed if !PAGE_PRESENT.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 5a45da02

arch/arc/mm/tlbex.S

+5 −5
Original line number Diff line number Diff line
@@ -277,15 +277,15 @@ ARC_ENTRY EV_TLBMissI 
	;----------------------------------------------------------------

	; VERIFY_PTE: Check if PTE permissions approp for executing code

	cmp_s   r2, VMALLOC_START

	mov.lo  r2, (_PAGE_PRESENT | _PAGE_U_READ | _PAGE_U_EXECUTE)

	mov.hs  r2, (_PAGE_PRESENT | _PAGE_K_READ | _PAGE_K_EXECUTE)

	mov.lo  r2, (_PAGE_PRESENT | _PAGE_U_EXECUTE)

	mov.hs  r2, (_PAGE_PRESENT | _PAGE_K_EXECUTE)



	and     r3, r0, r2  ; Mask out NON Flag bits from PTE

	xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )

	bnz     do_slow_path_pf



	; Let Linux VM know that the page was accessed

	or      r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED)  ; set Accessed Bit

	or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit

	st_s    r0, [r1]                ; Write back PTE



	CONV_PTE_TO_TLB
@@ -345,7 +345,7 @@ ARC_ENTRY EV_TLBMissD 
	;----------------------------------------------------------------

	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty

	lr      r3, [ecr]

	or      r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED) ; Accessed bit always

	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always

	btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?

	or.nz   r0, r0, _PAGE_MODIFIED        ; if Write, set Dirty bit as well

	st_s    r0, [r1]                      ; Write back PTE

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