Commit c3dd029c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-fixes-5.3-2019-08-28' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



drm-fixes-5.3-2019-08-28:

amdgpu:
- Fix GFXOFF regression for PCO and RV2
- Fix missing fence reference
- Fix VG20 power readings on certain SMU firmware versions
- Fix dpm level setup for VG20
- Add an ATPX laptop quirk

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190829022925.32678-1-alexander.deucher@amd.com
parents db26d53c 41940ff5

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

+1 −0
Original line number Diff line number Diff line
@@ -574,6 +574,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = { 
	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0, 0, 0, 0, 0 },

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+15 −12
Original line number Diff line number Diff line
@@ -534,22 +534,25 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 
			       struct drm_sched_entity *entity)

{

	struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);

	unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1);

	struct dma_fence *other = centity->fences[idx];

	struct dma_fence *other;

	unsigned idx;

	long r;



	spin_lock(&ctx->ring_lock);

	idx = centity->sequence & (amdgpu_sched_jobs - 1);

	other = dma_fence_get(centity->fences[idx]);

	spin_unlock(&ctx->ring_lock);



	if (!other)

		return 0;



	if (other) {

		signed long r;

	r = dma_fence_wait(other, true);

		if (r < 0) {

			if (r != -ERESTARTSYS)

	if (r < 0 && r != -ERESTARTSYS)

		DRM_ERROR("Error (%ld) waiting for fence!\n", r);



	dma_fence_put(other);

	return r;

}

	}



	return 0;

}



void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)

{

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+7 −7
Original line number Diff line number Diff line
@@ -596,14 +596,14 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 
	case CHIP_VEGA20:

		break;

	case CHIP_RAVEN:

		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)

			break;

		if ((adev->gfx.rlc_fw_version != 106 &&

		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)

			&&((adev->gfx.rlc_fw_version != 106 &&

			     adev->gfx.rlc_fw_version < 531) ||

			    (adev->gfx.rlc_fw_version == 53815) ||

			    (adev->gfx.rlc_feature_version < 1) ||

		    !adev->gfx.rlc.is_rlc_v2_1)

			    !adev->gfx.rlc.is_rlc_v2_1))

			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;



		if (adev->pm.pp_feature & PP_GFXOFF_MASK)

			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |

				AMD_PG_SUPPORT_CP |

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+59 −7
Original line number Diff line number Diff line
@@ -2101,6 +2101,10 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, 
	if (ret)

		return ret;



	/* For the 40.46 release, they changed the value name */

	if (hwmgr->smu_version == 0x282e00)

		*query = metrics_table.AverageSocketPower << 8;

	else

		*query = metrics_table.CurrSocketPower << 8;



	return ret;
@@ -2349,12 +2353,16 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) 
		data->dpm_table.soc_table.dpm_state.soft_max_level =

		data->dpm_table.soc_table.dpm_levels[soft_level].value;



	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);

	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload boot level to highest!",

			return ret);



	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);

	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload dpm max level to highest!",

			return ret);
@@ -2387,12 +2395,16 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) 
		data->dpm_table.soc_table.dpm_state.soft_max_level =

		data->dpm_table.soc_table.dpm_levels[soft_level].value;



	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);

	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload boot level to highest!",

			return ret);



	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);

	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload dpm max level to highest!",

			return ret);
@@ -2403,14 +2415,54 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) 


static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)

{

	struct vega20_hwmgr *data =

			(struct vega20_hwmgr *)(hwmgr->backend);

	uint32_t soft_min_level, soft_max_level;

	int ret = 0;



	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);

	/* gfxclk soft min/max settings */

	soft_min_level =

		vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));

	soft_max_level =

		vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));



	data->dpm_table.gfx_table.dpm_state.soft_min_level =

		data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;

	data->dpm_table.gfx_table.dpm_state.soft_max_level =

		data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;



	/* uclk soft min/max settings */

	soft_min_level =

		vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));

	soft_max_level =

		vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));



	data->dpm_table.mem_table.dpm_state.soft_min_level =

		data->dpm_table.mem_table.dpm_levels[soft_min_level].value;

	data->dpm_table.mem_table.dpm_state.soft_max_level =

		data->dpm_table.mem_table.dpm_levels[soft_max_level].value;



	/* socclk soft min/max settings */

	soft_min_level =

		vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));

	soft_max_level =

		vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));



	data->dpm_table.soc_table.dpm_state.soft_min_level =

		data->dpm_table.soc_table.dpm_levels[soft_min_level].value;

	data->dpm_table.soc_table.dpm_state.soft_max_level =

		data->dpm_table.soc_table.dpm_levels[soft_max_level].value;



	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload DPM Bootup Levels!",

			return ret);



	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);

	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |

						 FEATURE_DPM_UCLK_MASK |

						 FEATURE_DPM_SOCCLK_MASK);

	PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload DPM Max Levels!",

			return ret);

drivers/gpu/drm/amd/powerplay/vega20_ppt.c

+10 −1
Original line number Diff line number Diff line
@@ -3050,6 +3050,7 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu, 


static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)

{

	uint32_t smu_version;

	int ret = 0;

	SmuMetrics_t metrics;
@@ -3060,6 +3061,14 @@ static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value) 
	if (ret)

		return ret;



	ret = smu_get_smc_version(smu, NULL, &smu_version);

	if (ret)

		return ret;



	/* For the 40.46 release, they changed the value name */

	if (smu_version == 0x282e00)

		*value = metrics.AverageSocketPower << 8;

	else

		*value = metrics.CurrSocketPower << 8;



	return 0;

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