Commit c3bb8a9f authored Sep 28, 2020 by Kan Liang Committed by Peter Zijlstra Sep 29, 2020

perf/x86/msr: Add Jasper Lake support



The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of perf MSR, there is nothing changed compared with
Elkhart Lake.
Share the code path with Elkhart Lake.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-2-git-send-email-kan.liang@linux.intel.com

parent dbfd6388

arch/x86/events/msr.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
		case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
		case INTEL_FAM6_ATOM_TREMONT_D:
		case INTEL_FAM6_ATOM_TREMONT:
		case INTEL_FAM6_ATOM_TREMONT_L:

		case INTEL_FAM6_XEON_PHI_KNL:
		case INTEL_FAM6_XEON_PHI_KNM:

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