Commit c3b9ab5d authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: dts: imx7d-pico: Describe the Wifi clock



The Wifi chip should be clocked by a 32kHz clock coming from i.MX7D
CLKO2 output pin, so describe the pinmux and clock hierarchy in the
device tree to allow the Wifi chip to be properly clocked.

Managed to successfully test Wifi with such change. Used the standard
nvram.txt file provided by TechNexion, which selects an external 32kHz
clock for the Wifi chip by default.

Fixes: 99a52450 ("ARM: dts: imx7d-pico: Add Wifi support")
Suggested-by: default avatarArend van Spriel <arend.vanspriel@broadcom.com>
Tested-by: default avatarOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 512cab3e
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+21 −1
Original line number Diff line number Diff line
@@ -100,6 +100,19 @@
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	usdhc2_pwrseq: usdhc2_pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
		clock-names = "ext_clock";
	};
};

&clks {
	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
			  <&clks IMX7D_CLKO2_ROOT_DIV>;
	assigned-clock-parents = <&clks IMX7D_CKIL>;
	assigned-clock-rates = <0>, <32768>;
};

&i2c4 {
@@ -199,12 +212,13 @@

&usdhc2 { /* Wifi SDIO */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_ap6212>;
	mmc-pwrseq = <&usdhc2_pwrseq>;
	status = "okay";
};

@@ -301,6 +315,12 @@
};

&iomuxc_lpsr {
	pinctrl_wifi_clk: wificlkgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2	0x7d
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74