Commit c362aecd authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
Browse files

[ARM] 4442/1: OSIRIS: Fix CPLD register definitions 



Fix the CPLD register definitions to correctly mirror the
documentation

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 5d4cae5f

arch/arm/mach-s3c2440/mach-osiris.c

+14 −4
Original line number Diff line number Diff line
@@ -65,6 +65,11 @@ static struct map_desc osiris_iodesc[] __initdata = { 
  /* CPLD control registers */



  {

	  .virtual	= (u32)OSIRIS_VA_CTRL0,

	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),

	  .length	= SZ_16K,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)OSIRIS_VA_CTRL1,

	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),

	  .length	= SZ_16K,
@@ -74,6 +79,11 @@ static struct map_desc osiris_iodesc[] __initdata = { 
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),

	  .length	= SZ_16K,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)OSIRIS_VA_IDREG,

	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),

	  .length	= SZ_16K,

	  .type		= MT_DEVICE,

  },

};
@@ -195,13 +205,13 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) 
	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",

		 slot, set, set->nr_map);



	tmp = __raw_readb(OSIRIS_VA_CTRL1);

	tmp &= ~OSIRIS_CTRL1_NANDSEL;

	tmp = __raw_readb(OSIRIS_VA_CTRL0);

	tmp &= ~OSIRIS_CTRL0_NANDSEL;

	tmp |= slot;



	pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);



	__raw_writeb(tmp, OSIRIS_VA_CTRL1);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

}



static struct s3c2410_platform_nand osiris_nand_info = {

include/asm-arm/arch-s3c2410/osiris-cpld.h

+8 −6
Original line number Diff line number Diff line
@@ -14,12 +14,14 @@ 
#ifndef __ASM_ARCH_OSIRISCPLD_H

#define __ASM_ARCH_OSIRISCPLD_H



/* CTRL1 - NAND WP control */

/* CTRL0 - NAND WP control */



#define OSIRIS_CTRL1_NANDSEL		(0x3)

#define OSIRIS_CTRL1_BOOT_INT		(1<<3)

#define OSIRIS_CTRL1_PCMCIA		(1<<4)

#define OSIRIS_CTRL1_PCMCIA_nWAIT	(1<<6)

#define OSIRIS_CTRL1_PCMCIA_nIOIS16	(1<<7)

#define OSIRIS_CTRL0_NANDSEL		(0x3)

#define OSIRIS_CTRL0_BOOT_INT		(1<<3)

#define OSIRIS_CTRL0_PCMCIA		(1<<4)

#define OSIRIS_CTRL0_PCMCIA_nWAIT	(1<<6)

#define OSIRIS_CTRL0_PCMCIA_nIOIS16	(1<<7)



#define OSIRIS_ID_REVMASK		(0x7)



#endif /* __ASM_ARCH_OSIRISCPLD_H */

include/asm-arm/arch-s3c2410/osiris-map.h

+11 −8
Original line number Diff line number Diff line
@@ -24,16 +24,19 @@ 


/* we put the CPLD registers next, to get them out of the way */



#define OSIRIS_VA_CTRL1	    OSIRIS_IOADDR(0x00000000)

#define OSIRIS_PA_CTRL1	    (OSIRIS_PA_CPLD)

#define OSIRIS_VA_CTRL0		OSIRIS_IOADDR(0x00000000)

#define OSIRIS_PA_CTRL0		(OSIRIS_PA_CPLD)



#define OSIRIS_VA_CTRL2	    OSIRIS_IOADDR(0x00100000)

#define OSIRIS_PA_CTRL2	    (OSIRIS_PA_CPLD + (1<<23))

#define OSIRIS_VA_CTRL1		OSIRIS_IOADDR(0x00100000)

#define OSIRIS_PA_CTRL1		(OSIRIS_PA_CPLD + (1<<23))



#define OSIRIS_VA_CTRL3	    OSIRIS_IOADDR(0x00200000)

#define OSIRIS_VA_CTRL2		OSIRIS_IOADDR(0x00200000)

#define OSIRIS_PA_CTRL2		(OSIRIS_PA_CPLD + (2<<23))



#define OSIRIS_VA_CTRL3		OSIRIS_IOADDR(0x00300000)

#define OSIRIS_PA_CTRL3		(OSIRIS_PA_CPLD + (2<<23))



#define OSIRIS_VA_CTRL4	    OSIRIS_IOADDR(0x00300000)

#define OSIRIS_PA_CTRL4	    (OSIRIS_PA_CPLD + (3<<23))

#define OSIRIS_VA_IDREG		OSIRIS_IOADDR(0x00700000)

#define OSIRIS_PA_IDREG		(OSIRIS_PA_CPLD + (7<<23))



#endif /* __ASM_ARCH_OSIRISMAP_H */

CRA Git | Maintained and supported by SUSTech CRA and CCSE