Commit c341a108 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Only define APG0 and APG1 



Since the 8xx implements hardware page table walk assistance,
the PGD entries always point to a 4k aligned page, so the 2 upper
bits of the APG are not clobbered anymore and remain 0. Therefore
only APG0 and APG1 are used and need a definition. We set the
other APG to the lowest permission level.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent e2fb9f54

arch/powerpc/include/asm/nohash/32/mmu-8xx.h

+6 −6
Original line number Diff line number Diff line
@@ -35,11 +35,11 @@ 
 * Then we use the APG to say whether accesses are according to Page rules or

 * "all Supervisor" rules (Access to all)

 * Therefore, we define 2 APG groups. lsb is _PMD_USER

 * 0 => No user => 01 (all accesses performed according to page definition)

 * 0 => Kernel => 01 (all accesses performed according to page definition)

 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)

 * We define all 16 groups so that all other bits of APG can take any value

 * 2-16 => NA => 11 (all accesses performed as user iaw page definition)

 */

#define MI_APG_INIT	0x44444444

#define MI_APG_INIT	0x4fffffff



/* The effective page number register.  When read, contains the information

 * about the last instruction TLB miss.  When MI_RPN is written, bits in
@@ -108,11 +108,11 @@ 
 * Then we use the APG to say whether accesses are according to Page rules or

 * "all Supervisor" rules (Access to all)

 * Therefore, we define 2 APG groups. lsb is _PMD_USER

 * 0 => No user => 01 (all accesses performed according to page definition)

 * 0 => Kernel => 01 (all accesses performed according to page definition)

 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)

 * We define all 16 groups so that all other bits of APG can take any value

 * 2-16 => NA => 11 (all accesses performed as user iaw page definition)

 */

#define MD_APG_INIT	0x44444444

#define MD_APG_INIT	0x4fffffff



/* The effective page number register.  When read, contains the information

 * about the last instruction TLB miss.  When MD_RPN is written, bits in

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